Selected word line dependent select gate voltage during program

ABSTRACT

Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.

BACKGROUND

The present disclosure relates to non-volatile storage.

Semiconductor memory has become increasingly popular for use in variouselectronic devices. For example, non-volatile semiconductor memory isused in cellular telephones, digital cameras, personal digitalassistants, mobile computing devices, non-mobile computing devices andother devices. Electrically Erasable Programmable Read Only Memory(EEPROM) and flash memory are among the most popular non-volatilesemiconductor memories. With flash memory, also a type of EEPROM, thecontents of the whole memory array, or of a portion of the memory, canbe erased in one step, in contrast to the traditional, full-featuredEEPROM.

Both the traditional EEPROM and the flash memory utilize a floating gatethat is positioned above and insulated from a channel region in asemiconductor substrate. The floating gate is positioned between thedrain and source diffusion regions. A control gate is provided over andinsulated from the floating gate. The threshold voltage (V_(TH)) of thetransistor thus formed is controlled by the amount of charge that isretained on the floating gate. That is, the minimum amount of voltagethat must be applied to the control gate before the transistor is turnedon to permit conduction between its drain and source is controlled bythe level of charge on the floating gate.

In a NAND architecture, memory cells are arranged as NAND strings. ANAND string includes memory cells (each including a floating gate)connected in series over a substrate. At each end of the NAND stringthere is a select transistor (also referred to as a select gate). One ofthe select transistors (source side select transistor)connects/disconnects the NAND string to a source line that is common toa large group of NAND strings. Each NAND string is associated with onebit line. The other select transistor (drain side select transistor)connects/disconnects its NAND string to a bit line. In one approach, amemory cell on a NAND string may be read by applying a voltage to itscontrol gate and sensing a signal on the bit line.

Typically, a program voltage V_(PGM) applied to the control gate duringa program operation is applied as a series of pulses that increase inmagnitude as programming progresses. In one possible approach, themagnitude of the pulses is increased with each successive pulse by apredetermined step size, e.g., 0.2-0.4 V. V_(PGM) can be applied to thecontrol gates of flash memory cells. In the periods between the programpulses, verify operations are carried out. That is, the programminglevel of each element of a group of cells being programmed in parallelis read between successive programming pulses to determine whether it isequal to or greater than a verify level to which the element is beingprogrammed.

After a given memory cell on the word line selected for programmingreaches its intended threshold voltage, programming may be inhibited forthat memory cell. In one approach, programming is inhibited by applyingan inhibit voltage to the bit line associated with the NAND string. Thevoltage applied to the gate of the drain side select transistor shouldbe low enough to keep the transistor off, such that the channel of aninhibited NAND string may float. Likewise, the voltage applied to thegate of the source side select transistor should be low enough to keepthe transistor off, such that the channel of an inhibited NAND stringmay float. Also, a voltage is applied to control gates of unselectedmemory cells, which boosts the voltage in the channel region of thememory cells on inhibited NAND strings. This boosted channel voltagehelps to reduce or eliminate program disturb.

However, it is possible for the channel voltage of the inhibited NANDstrings to drop, which can result in program disturb. One possiblereason for the drop in channel voltage is leakage of current from aboosted channel. For example, the current could leak across the channelof either select transistor.

One type of leakage is due to punch-through conduction across a selecttransistor. Punch-through conduction may occur due to the difference inthe drain to source voltage across the channel of a select gatetransistor. As memory arrays continue to scale down in size, the channellength of select gate transistors is getting shorter. Therefore, shortchannel effects such as punch-through conduction may become moreproblematic.

Another type of leakage from the channel of inhibited NAND strings mayarise due to drain induced barrier lowering (DIBL). DIBL may cause theV_(TH) of the select transistors to drop. If the V_(TH) of a selecttransistor of an inhibited NAND string is lowered enough, it may turnon, at least weakly. If this happens, then current may leak from theboosted channel across the channel of the select transistor, therebydischarging the voltage of the NAND string channel. Consequently,program disturb could occur.

Gate induced drain leakage (GIDL) is another problem that may causeprogram disturb. GIDL refers to charge carriers leaking into the channelfrom a select transistor as a result of a voltage applied to the gate ofone of the select transistors. These charge carriers (e.g., electrons)may be accelerated in an E-field in the channel of the NAND string.Program disturb may result due to hot carrier injection of the electronsfrom the channel to a floating gate of a memory cell.

It is desirable to prevent or reduce program disturb, which may arisefrom a variety of causes including, but not limited to, punch-throughconduction, DIBL, and GIDL.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of a NAND string.

FIG. 1B is an equivalent circuit diagram of the NAND string of FIG. 1A.

FIG. 2 is a circuit diagram depicting three NAND strings.

FIG. 3 depicts a cross-sectional view of a NAND string formed on asubstrate.

FIG. 4 illustrates a non-volatile storage device.

FIG. 5A depicts an exemplary structure of memory cell array.

FIG. 5B is a block diagram of an individual sense block.

FIG. 6A depicts an example set of Vt distributions.

FIG. 6B depicts an example set of Vt distributions.

FIG. 7A depicts an example set of threshold voltage distributions for afour-state memory device in which each storage element stores two bitsof data.

FIG. 7B shows a series of program pulses that may be used to program adistribution of FIG. 7A.

FIG. 8 is a flowchart describing one embodiment of a programmingprocess.

FIGS. 9(A)-9(H) are timing diagrams illustrating voltages during programoperations, according to one embodiment.

FIG. 10 is a graph that shows Erase-to-A failures versus program pulsewidth for selected word lines in various positions along a NAND string.

FIG. 11A, FIG. 11B, and FIG. 11C show example graphs of Vth distributionwidths versus program pulse widths.

FIG. 12 shows a graph of program loop count versus program pulse width.

FIGS. 13A and 13B are graphs that show word lines RC dependence

FIG. 14 is a flowchart of one embodiment of a process of programmingnon-volatile storage using a programming voltage having a pulse widththat depends on the width of the selected word line.

FIG. 15 is a flowchart of one embodiment of a process of programmingnon-volatile storage using a programming voltage having a pulse widththat depends on the location of the selected word line.

FIG. 16 is a flowchart of one embodiment of a process of programmingnon-volatile storage that involves determining a width of a programpulse.

FIG. 17 is a flowchart of a process of determining suitable pulse widthsfor programming signals for word lines, depending on their position.

FIG. 18A shows a boosted NAND string having SGS leakage current and SGDleakage current.

FIG. 18B shows a portion of the NAND string near the SGS transistor toshows GIDL effect.

FIG. 18C shows a portion of the NAND string near the SGD transistor toshows GIDL effect.

FIG. 19 is a flowchart of one embodiment of programming non-volatilestorage that may counteract punch-through leakage.

FIG. 20A shows relative values for Vcel_src versus word lines inaccordance with one embodiment.

FIG. 20B depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which the voltage applied to thecommon source line depends on the location of the selected word line.

FIG. 21A shows inhibited bit line voltage versus word line for oneembodiment.

FIG. 21B shows inhibited bit line voltage versus word line for oneembodiment.

FIG. 21C shows inhibited bit line voltage versus word line for oneembodiment.

FIG. 21D shows an inhibited NAND string with a boosting scheme referredto as Erase Area Self Boosting (EASB).

FIG. 21E depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which a bit line voltage depends onthe selected word line.

FIG. 22A depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which the magnitude of the voltageSGS depends on the location of the selected word line.

FIG. 22B shows voltage applied to a gate of a source side selecttransistor versus word line for one embodiment.

FIG. 23A depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which the magnitude of the voltageSGD depends on the location of the selected word line.

FIG. 23B shows voltage applied to a gate of a drain side selecttransistor versus word line for one embodiment.

FIG. 24 depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which a voltage applied to bit linesdepends on the location of the selected word line.

FIG. 25 depicts a flowchart of one embodiment of a process ofprogramming non-volatile storage in which the voltage applied to a gateof a select transistor depends on the location of the selected wordline.

FIG. 26A shows relative values for Vsgs versus word lines in accordancewith one embodiment.

FIG. 26B shows relative values for Vsgd versus word lines in accordancewith one embodiment.

FIG. 27A and FIG. 27B shows possible effects of DIBL on the Vth of SGStransistors.

FIG. 28 shows a possible Vsgd window.

FIG. 29 shows possible word line dependence of the lower-cliff andupper-cliff of Vsgd window.

FIG. 30A and FIG. 30B show possible failure bit count versus word line.

DETAILED DESCRIPTION

The present disclosure provides methods and devices for operatingnon-volatile storage. In some embodiments, one or more programmingconditions depend on the location of the word line that is selected forprogramming. Applying selected word line dependent program conditionsmay reduce or eliminate program disturb.

A word line may be considered to be an “edge word line” or a “middleword line.” An “edge word line” is defined herein as those within “n”word lines of the lowest or highest word line that is used to store useror system data. At least the lowest and highest word lines used to storeuser or system data are considered to be edge word lines. There may beone or more edge word lines at each end of a NAND string. The word linesthat are considered to be edge word lines are not necessarily fixed fora given memory array. Rather, the particular context may determinewhether a word line is considered to be an edge word line. A “middleword line” is defined herein as any word line that is used to store useror system data other than edge word lines.

In one embodiment, the width (or duration) of a programming pulsedepends on the word line that is selected for programming. In oneembodiment, the duration of a programming pulse depends on a physicalcharacteristic of the selected word line, such as its width. In oneembodiment, the duration of a programming pulse depends on the locationof the selected word line on a NAND string. As one example, a shorterpulse width may be used for the programming signal when programming edgeword lines.

In one embodiment, the voltage applied to a common source line dependson the location of the word line that is selected for programming. Thismay prevent or reduce punch-through conduction, which may depend on thelocation of the selected word line. In one embodiment, the voltageapplied to the common source line is higher for lower selected wordlines than the voltage used for higher selected word lines.

In one embodiment, the voltage applied to bit lines of unselected NANDstrings depends on the location of the word line that is selected forprogramming. This may prevent or reduce punch-through conduction, whichmay depend on the location of the selected word line. In one embodiment,the voltage applied to bit lines associated with unselected NAND stringsis higher for lower selected word lines than the voltage used for higherselected word lines. In one embodiment, a higher voltage is used whenprogramming edge word lines that are near the drain end of the NANDstring.

In one embodiment, the voltage applied to the gate of a selecttransistor of a NAND string depends on the location of the word linethat is selected for programming. This could be either a source side ordrain side select transistor. This may prevent or reduce program disturbthat could result due to DIBL. In one embodiment, a negative bias isapplied to the gate of a source side select transistor when programmingat least some of the word lines. In one embodiment, progressively lowervoltages are used for the gate of the drain side select transistor whenprogramming progressively higher word lines.

In one embodiment, the voltage applied to the gate of a source sideselect transistor depends on the location of the word line that isselected for programming. This may prevent or reduce GIDL, which maydepend on the location of the selected word line. In one embodiment, thevoltage applied to the gate of a drain side select transistor depends onthe location of the word line that is selected for programming. This mayprevent or reduce GIDL, which may depend on the location of the selectedword line. In one embodiment, a higher voltage is applied to the gate ofa select transistor when the selected word line is an edge word linenear that select transistor.

In one embodiment, the voltage applied to one or more bit lines dependson the location of the word line that is selected for programming. Thismay further help to prevent or reduce program disturb associated withGIDL. In one embodiment, the voltage applied to one or more bit linesassociated with selected NAND strings depends on the location of theword line that is selected for programming. In one embodiment, thevoltage applied to one or more bit lines associated with unselected NANDstrings depends on the location of the word line that is selected forprogramming. In one embodiment, the voltage applied to one or more bitlines associated with NAND strings in a slow programming mode depends onthe location of the word line that is selected for programming.

One example of a memory system suitable for implementing embodimentsuses a NAND flash memory structure, which includes arranging multipletransistors in series between two select gates. The transistors inseries and the select gates are referred to as a NAND string. FIG. 1A isa top view showing one NAND string. FIG. 1B is an equivalent circuitthereof. The NAND string depicted in FIGS. 1A and 1B includes fourtransistors, 100, 102, 104 and 106, in series and sandwiched between afirst select gate 120 and a second select gate 122. Select gate 120gates the NAND string connection to bit line 126. Select gate 122 gatesthe NAND string connection to source line 128. Select gate 120 iscontrolled by applying the appropriate voltages to control gate 120CG.Select gate 122 is controlled by applying the appropriate voltages tocontrol gate 122CG. Each of the transistors 100, 102, 104 and 106 has acontrol gate and a floating gate. Transistor 100 has control gate 100CGand floating gate 100FG. Transistor 102 includes control gate 102CG andfloating gate 102FG. Transistor 104 includes control gate 104CG andfloating gate 104FG. Transistor 106 includes a control gate 106CG andfloating gate 106FG. Control gate 100CG is connected to (or is) wordline WL3, control gate 102CG is connected to word line WL2, control gate104CG is connected to word line WL1, and control gate 106CG is connectedto word line WL0. In one embodiment, transistors 100, 102, 104 and 106are each storage elements, also referred to as memory cells. In otherembodiments, the storage elements may include multiple transistors ormay be different than that depicted in FIGS. 1A and 1B. Select gate 120is connected to select line SGD. Select gate 122 is connected to selectline SGS. In one embodiment, select gates 120 and 122 are eachimplemented with a “select transistor.” Thus, select gate 120 may bereferred to as a “drain side select transistor,” (or SGD transistor) andselect gate 122 may be referred to as a “source side select transistor”(or SGS transistor).

FIG. 2 is a circuit diagram depicting three NAND strings. A typicalarchitecture for a flash memory system using a NAND structure willinclude several NAND strings. For example, three NAND strings 320, 340and 360 are shown in a memory array having many more NAND strings. Eachof the NAND strings includes two select gates and four storage elements.While four storage elements are illustrated for simplicity, modern NANDstrings can have thirty-two, sixty-four, or more storage elements, forinstance.

For example, NAND string 320 includes select gates 322 and 327, andstorage elements 323-326, NAND string 340 includes select gates 342 and347, and storage elements 343-346, NAND string 360 includes select gates362 and 367, and storage elements 363-366. Each NAND string is connectedto the source line by its select gates (e.g., select gates 327, 347 or367). A selection line SGS is used to control the source side selectgates. In one embodiment, the various NAND strings 320, 340 and 360 areconnected to respective bit lines 321, 341 and 361, by selecttransistors. In one embodiment, the select transistors are in the selectgates 322, 342, 362, etc. In one embodiment, the select transistors formthe select gates 322, 342, 362. These select transistors are controlledby a drain select line SGD. In other embodiments, the select lines donot necessarily need to be in common among the NAND strings; that is,different select lines can be provided for different NAND strings. Wordline WL3 is connected to the control gates for storage elements 323, 343and 363. Word line WL2 is connected to the control gates for storageelements 324, 344 and 364. Word line WL1 is connected to the controlgates for storage elements 325, 345 and 365. Word line WL0 is connectedto the control gates for storage elements 326, 346 and 366. As can beseen, each bit line and the respective NAND string comprise the columnsof the array or set of storage elements. The word lines (WL3, WL2, WL1and WL0) comprise the rows of the array or set. Each word line connectsthe control gates of each storage element in the row. Or, the controlgates may be provided by the word lines themselves. For example, wordline WL2 provides the control gates for storage elements 324, 344 and364. In practice, there can be thousands of storage elements on a wordline.

Each storage element can store data. For example, when storing one bitof digital data, the range of possible threshold voltages (V_(TH)) ofthe storage element is divided into two ranges which are assignedlogical data “1” and “0.” In one example of a NAND type flash memory,the V_(TH) is negative after the storage element is erased, and definedas logic “1.” The V_(TH) after a program operation is positive anddefined as logic “0.” When the V_(TH) is negative and a read isattempted, the storage element will turn on to indicate logic “1” isbeing stored. When the V_(TH) is positive and a read operation isattempted, the storage element will not turn on, which indicates thatlogic “0” is stored. A storage element can also store multiple levels ofinformation, for example, multiple bits of digital data. In this case,the range of V_(TH) value is divided into the number of levels of data.For example, if four levels of information are stored, there will befour V_(TH) ranges assigned to the data values “11”, “10”, “01”, and“00.” In one example of a NAND type memory, the V_(TH) after an eraseoperation is negative and defined as “11”. Positive V_(TH) values areused for the states of “10”, “01”, and “00.” The specific relationshipbetween the data programmed into the storage element and the thresholdvoltage ranges of the element depends upon the data encoding schemeadopted for the storage elements. For example, U.S. Pat. Nos. 6,222,762and 7,237,074, both of which are incorporated herein by reference intheir entirety, describe various data encoding schemes for multi-stateflash storage elements.

Relevant examples of NAND type flash memories and their operation areprovided in U.S. Pat. Nos. 5,386,422; 5,570,315; 5,774,397; 6,046,935;6,456,528; and 6,522,580, each of which is incorporated herein byreference.

When programming a flash storage element, a program voltage is appliedto the control gate of the storage element, and the bit line associatedwith the storage element is grounded. Electrons from the channel areinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and theV_(TH) of the storage element is raised. To apply the program voltage tothe control gate of the storage element being programmed, that programvoltage is applied on the appropriate word line. As discussed above, onestorage element in each of the NAND strings share the same word line.For example, when programming storage element 324 of FIG. 2, the programvoltage will also be applied to the control gates of storage elements344 and 364.

FIG. 3 depicts a cross-sectional view of a NAND string formed on asubstrate. The view is simplified and not to scale. The NAND string 400includes a source-side select gate (or SGS transistor) 406, a drain-sideselect gate (or SGD transistor) 424, and eight storage elements 408,410, 412, 414, 416, 418, 420 and 422, formed on a substrate 490. Anumber of source/drain regions, one example of which is sourcedrain/region 430, are provided on either side of each storage element.In one embodiment, the substrate 490 employs a triple-well technologywhich includes an array p-well region 492 within an array n-well region494, which in turn is within a p-type substrate region 496. The NANDstring and its non-volatile storage elements can be formed, at least inpart, on the array p-well region 492.

A voltage V_(SOURCE) is provided to a source line contact 404. Thesource line contact has an electrical connection to the diffusion region431 of SGS transistor 406. A bit line voltage V_(BL) is supplied to bitline contact 426, which is in electrical contact with the diffusionregion 432 of SGD transistor 424. Note that diffusion region 431 may bereferred to herein as a source. Note that diffusion region 432 may bereferred to herein as a drain; however, it will be understood that undersome conditions (such as when the voltage of the channel of the NANDstring is boosted) the diffusion region 432 may be at a lower voltagethan the terminal on the other side of the channel of the SGD transistor424. Voltages, such as body bias voltages, can also be applied to thearray p-well region 492 via a terminal 402 and/or to the array n-wellregion 494 via a terminal 403.

During a program operation, a control gate voltage V_(PGM) is providedon a selected word line, in this example, WL3, which is associated withstorage element 414. Further, recall that the control gate of a storageelement may be provided as a portion of the word line. For example, WL0,WL1, WL2, WL3, WL4, WL5, WL6 and WL7 can extend via the control gates ofstorage elements 408, 410, 412, 414, 416, 418, 420 and 422,respectively. A pass voltage, V_(PASS) is applied to the remaining wordlines associated with NAND string 400, in one possible boosting scheme.V_(SGS) and V_(SGD) are applied to the select gates 406 and 424,respectively.

FIG. 4 illustrates a non-volatile storage device 210 that may includeone or more memory die or chips 212. Memory die 212 includes an array(two-dimensional or three dimensional) of memory cells 200, controlcircuitry 220, and read/write circuits 230A and 230B. In one embodiment,access to the memory array 200 by the various peripheral circuits isimplemented in a symmetric fashion, on opposite sides of the array, sothat the densities of access lines and circuitry on each side arereduced by half. The read/write circuits 230A and 230B include multiplesense blocks 300 which allow a page of memory cells to be read orprogrammed in parallel. The memory array 200 is addressable by wordlines via row decoders 240A and 240B and by bit lines via columndecoders 242A and 242B. In a typical embodiment, a controller 244 isincluded in the same memory device 210 (e.g., a removable storage cardor package) as the one or more memory die 212. Commands and data aretransferred between the host and controller 244 via lines 232 andbetween the controller and the one or more memory die 212 via lines 234.One implementation can include multiple chips 212.

Control circuitry 220 cooperates with the read/write circuits 230A and230B to perform memory operations on the memory array 200. The controlcircuitry 220 includes a state machine 222, an on-chip address decoder224 and a power control module 226. The state machine 222 provideschip-level control of memory operations. The on-chip address decoder 224provides an address interface to convert between the address that isused by the host or a memory controller to the hardware address used bythe decoders 240A, 240B, 242A, and 242B. The power control module 226controls the power and voltages supplied to the word lines and bit linesduring memory operations. In one embodiment, power control module 226includes one or more charge pumps that can create voltages larger thanthe supply voltage.

In one embodiment, one or any combination of control circuitry 220,power control circuit 226, decoder circuit 224, state machine circuit222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A,decoder circuit 240B, read/write circuits 230A, read/write circuits230B, and/or controller 244 can be referred to as one or more managingcircuits.

FIG. 5A depicts an example structure of memory cell array 200. In oneembodiment, the array of memory cells is divided into M blocks of memorycells. As is common for flash EEPROM systems, the block is the unit oferase. That is, each block contains the minimum number of memory cellsthat are erased together. Each block is typically divided into a numberof pages. A page is a unit of programming. One or more pages of data aretypically stored in one row of memory cells. A page can store one ormore sectors. A sector includes user data and overhead data. Overheaddata typically includes an Error Correction Code (ECC) that has beencalculated from the user data of the sector. A portion of the controller(described below) calculates the ECC when data is being programmed intothe array, and also checks it when data is being read from the array. Inone embodiment, the controller 244 is able to correct a certain numberof misreads, based on the ECC.

Alternatively, the ECCs and/or other overhead data are stored indifferent pages, or even different blocks, than the user data to whichthey pertain. A sector of user data is typically 512 bytes,corresponding to the size of a sector in magnetic disk drives. A largenumber of pages form a block, anywhere from 8 pages, for example, up to32, 64, 128 or more pages. Different sized blocks and arrangements canalso be used.

In another embodiment, the bit lines are divided into odd bit lines andeven bit lines. In an odd/even bit line architecture, memory cells alonga common word line and connected to the odd bit lines are programmed atone time, while memory cells along a common word line and connected toeven bit lines are programmed at another time.

FIG. 5A shows more details of block i of memory array 200. Block iincludes X+1 bit lines and X+1 NAND strings. Block i also includes 64data word lines (WL0-WL63), 2 dummy word lines (WL_d0 and WL_d1), adrain side select line (SGD) and a source side select line (SGS). Oneterminal of each NAND string is connected to a corresponding bit linevia a drain select gate (connected to select line SGD), and anotherterminal is connected to the source line via a source select gate(connected to select line SGS). Because there are sixty four data wordlines and two dummy word lines, each NAND string includes sixty fourdata memory cells and two dummy memory cells. In other embodiments, theNAND strings can have more or fewer than 64 data memory cells and twodummy memory cells. Data memory cells can store user or system data.Dummy memory cells are typically not used to store user or system data.Some embodiments do not include dummy memory cells.

FIG. 5B is a block diagram of an individual sense block 300 partitionedinto a core portion, referred to as a sense module 580, and a commonportion 590. In one embodiment, there will be a separate sense module580 for each bit line and one common portion 590 for a set of multiplesense modules 580. In one example, a sense block will include one commonportion 590 and eight sense modules 580. Each of the sense modules in agroup will communicate with the associated common portion via a data bus572. For further details, refer to U.S. Patent Application Publication2006/0140007, which is incorporated herein by reference in its entirety.

Sense module 580 comprises sense circuitry 570 that determines whether aconduction current in a connected bit line is above or below apredetermined threshold level. In some embodiments, sense module 580includes a circuit commonly referred to as a sense amplifier. Sensemodule 580 also includes a bit line latch 582 that is used to set avoltage condition on the connected bit line. For example, apredetermined state latched in bit line latch 582 will result in theconnected bit line being pulled to a state designating program inhibit(e.g., V_(DD)).

Common portion 590 comprises a processor 592, a set of data latches 594and an I/O Interface 596 coupled between the set of data latches 594 anddata bus 520. Processor 592 performs computations. For example, one ofits functions is to determine the data stored in the sensed memory celland store the determined data in the set of data latches. The set ofdata latches 594 is used to store data bits determined by processor 592during a read operation. Data latches 594 may also be used to store databits imported from the data bus 520 during a program operation. Theimported data bits represent write data meant to be programmed into thememory. I/O interface 596 provides an interface between data latches 594and the data bus 520.

During read or sensing, the operation of the system is under the controlof state machine 222 that controls the supply of different control gatevoltages to the addressed cell. As it steps through the variouspredefined control gate voltages corresponding to the various memorystates supported by the memory, the sense module 580 may trip at one ofthese voltages and an output will be provided from sense module 580 toprocessor 592 via bus 572. At that point, processor 592 determines theresultant memory state by consideration of the tripping event(s) of thesense module and the information about the applied control gate voltagefrom the state machine via input lines 593. It then computes a binaryencoding for the memory state and stores the resultant data bits intodata latches 594. In another embodiment of the core portion, bit linelatch 582 serves double duty, both as a latch for latching the output ofthe sense module 580 and also as a bit line latch as described above.

It is anticipated that some implementations will include multipleprocessors 592. In one embodiment, each processor 592 will include anoutput line (not depicted in FIG. 5) such that each of the output linesis wired-OR'd together. In some embodiments, the output lines areinverted prior to being connected to the wired-OR line. Thisconfiguration enables a quick determination during the programverification process of when the programming process has completedbecause the state machine receiving the wired-OR line can determine whenall bits being programmed have reached the desired level. For example,when each bit has reached its desired level, a logic zero for that bitwill be sent to the wired-OR line (or a data one is inverted). When allbits output a data 0 (or a data one inverted), then the state machineknows to terminate the programming process. In embodiments where eachprocessor communicates with eight sense modules, the state machine may(in some embodiments) need to read the wired-OR line eight times, orlogic is added to processor 592 to accumulate the results of theassociated bit lines such that the state machine need only read thewired-OR line one time.

During program or verify, the data to be programmed is stored in the setof data latches 594 from the data bus 520. The program operation, underthe control of the state machine, comprises a series of programmingvoltage pulses (with increasing magnitudes) applied to the control gatesof the addressed memory cells. Each programming pulse is followed by averify process to determine if the memory cell has been programmed tothe desired state. Processor 592 monitors the verified memory staterelative to the desired memory state. When the two are in agreement,processor 592 sets the bit line latch 582 so as to cause the bit line tobe pulled to a state designating program inhibit. This inhibits the cellcoupled to the bit line from further programming even if it is subjectedto programming pulses on its control gate. In other embodiments theprocessor initially loads the bit line latch 582 and the sense circuitrysets it to an inhibit value during the verify process. In oneembodiment, the magnitude of the inhibit value depends on the locationof the selected word line.

Data latch stack 594 contains a stack of data latches corresponding tothe sense module. In one embodiment, there are 3-5 (or another number)data latches per sense module 580. In one embodiment, the latches areeach one bit. In some implementations (but not required), the datalatches are implemented as a shift register so that the parallel datastored therein is converted to serial data for data bus 520, and viceversa. In one embodiment, all the data latches corresponding to theread/write block of M memory cells can be linked together to form ablock shift register so that a block of data can be input or output byserial transfer. In particular, the bank of read/write modules isadapted so that each of its set of data latches will shift data in to orout of the data bus in sequence as if they are part of a shift registerfor the entire read/write block.

Additional information about the read operations and sense amplifierscan be found in (1) U.S. Pat. No. 7,196,931, “Non-Volatile Memory AndMethod With Reduced Source Line Bias Errors,”; (2) U.S. Pat. No.7,023,736, “Non-Volatile Memory And Method with Improved Sensing,”; (3)U.S. Pat. No. 7,046,568, “Memory Sensing Circuit and Method for LowVoltage Operation; (4) U.S. Pat. No. 7,196,928, “Compensating forCoupling During Read Operations of Non-Volatile Memory,” and (5) U.S.Pat. No. 7,327,619, “Reference Sense Amplifier For Non-Volatile Memory”.All five of the immediately above-listed patent documents areincorporated herein by reference in their entirety.

At the end of a successful programming process (with verification), thethreshold voltages of the memory cells should be within one or moredistributions of threshold voltages for programmed memory cells orwithin a distribution of threshold voltages for erased memory cells, asappropriate. FIG. 6A illustrates example Vt distributions correspondingto data states for the memory cell array when each memory cell storesthree bits of data. Other embodiment, however, may use more or fewerthan three bits of data per memory cell. FIG. 6A shows eight Vtdistributions corresponding to an Erase state and programmed states A-G.In one embodiment, the threshold voltages in the Erase state arenegative and the threshold voltages in the programmed states A-G arepositive.

However, the threshold voltages in one or more of programmed states A-Gmay be negative. Thus, in one embodiment, at least VrA is negative.Other voltages such as VvA, VrB, VvB, etc., may also be negative.

Between each of the data states are read reference voltages used forreading data from memory cells. For example, FIG. 6A shows readreference voltage VrA between the erase state and the A-state, and VrBbetween the A-state and B-state. By testing whether the thresholdvoltage of a given memory cell is above or below the respective readreference voltages, the system can determine what state the memory cellis in.

At or near the lower edge of each programmed state are verify referencevoltages. For example, FIG. 6A shows VvA for the A-state and VvB for theB-state. When programming memory cells to a given state, the system willtest whether those memory cells have a threshold voltage greater than orequal to the verify reference voltage.

FIG. 6B illustrates that Vt distributions can partially overlap sincethe error correction algorithm can handle a certain percentage of cellsthat are in error. Note that in some embodiments, at one point in timethe threshold voltage distribution may resemble FIG. 6A and at anothertime the threshold voltage distributions may overlap, as in FIG. 6B. Forexample, just after programming, the threshold voltage distribution mayresemble FIG. 6A. However, over time, the threshold voltages of memorycells may shift, such that there may be overlap.

Also note that contrary to the equal spacing/width of the depictedthreshold voltage distributions, various distributions may havedifferent widths/spacings in order to accommodate varying amounts ofsusceptibility to data retention loss.

In some embodiments, a “verify low” and a “verify high” referencevoltage is used. FIG. 7A depicts an example set of threshold voltagedistributions for a four-state memory device in which each storageelement stores two bits of data. A first threshold voltage distribution700 is provided for erased (Erased-state) storage elements. Threethreshold voltage distributions 702, 704 and 706 represent programmedstates A, B and C, respectively. In one embodiment, the thresholdvoltages in the Erased-state are negative, and the threshold voltages inthe A-, B- and C-states are positive.

Read reference voltages, VrA, VrB and VrC, are also provided for readingdata from storage elements. By testing whether the threshold voltage ofa given storage element is above or below VrA, VrB and VrC, the systemcan determine the state, e.g., the storage element is in.

Further, verify reference voltages, VvA, VvB, and VvC are provided. Whenprogramming storage elements to the A-state, B-state or C-state, thesystem will test whether those storage elements have a threshold voltagegreater than or equal to VvA, VvB or VvC, respectively. In oneembodiment, “verify low” reference voltages, VvaL, VvbL, and VvcL areprovided. Similar “verify low” reference voltages could also be used inembodiments with a different number of states.

In full sequence programming, storage elements can be programmed fromthe Erased-state directly to any of the programmed states A, B or C. Forexample, a population of storage elements to be programmed may first beerased so that all storage elements in the population are in theErased-state. A series of program pulses such as depicted in FIG. 7B isused to program storage elements directly into the A-, B- and C-states.While some storage elements are being programmed from the Erased-stateto the A-state, other storage elements are being programmed from theErased-state to the B-state and/or from the Erased-state to the C-state.Note that using a full sequence programming is not required.

One example of a slow programming mode uses low (offset) and high(target) verify levels for one or more data states. For example, VvaLand VvA are offset and target verify levels, respectively, for theA-state, and VvbL and VvB are offset and target verify levels,respectively, for the B-state. During programming, when the thresholdvoltage of a storage element which is being programmed to the A-state asa target state (e.g., an A-state storage element) exceeds VvaL, itsprogramming speed is slowed, such as by raising the bit line voltage toa level, e.g., 0.6-0.8 V, which is between a nominal program ornon-inhibit level, e.g., 0 V and a full inhibit level, e.g., 2-3 V. Themiddle value may be referred to as a quick pass write (QPW) value. Thisprovides greater accuracy by avoiding large step increases in thresholdvoltage. In some embodiments, values for one or more of the nominalprogram value, QPW value, and/or the inhibit value depend on thelocation of the word line that is selected for programming.

When the threshold voltage reaches VvA, the storage element is lockedout from further programming. Similarly, when the threshold voltage of aB-state storage element exceeds VvbL, its programming speed is slowed,and when the threshold voltage reaches VvB, the storage element islocked out from further programming. In one approach, a slow programmingmode is not used for the highest state since some overshoot is typicallyacceptable. Instead, the slow programming mode can be used for theprogrammed states, above the erased state, and below the highest state.

Moreover, in the example programming techniques discussed, the thresholdvoltage of a storage element is raised as it is programmed to a targetdata state. However, programming techniques can be used in which thethreshold voltage of a storage element is lowered as it is programmed toa target data state. Programming techniques which measure storageelement current can be used as well. The concepts herein can be adaptedto different programming techniques.

FIG. 7B depicts a series of program and verify pulses which are appliedto a selected word line during a programming operation. A programmingoperation may include multiple programming iterations, where eachiteration applies one or more program pulses (voltages) followed by oneor more verify voltages, to a selected word line. In one possibleapproach, the program voltages are stepped up in successive iterations.Moreover, the program voltages may include a first portion which has apass voltage (Vpass) level, e.g., 6-8 V, followed by a second portion ata program level, e.g., 12-25 V. For example, first, second, third andfourth program pulses 752, 754, 756 and 758 have program voltages ofVpgm1, Vpgm2, Vpgm3 and Vpgm4, respectively, and so forth. A set of oneor more verify voltages may be provided after each program pulse. Insome embodiments, there may be two or more verify pulses between theprogram pulses. For example, one pulse might be used to verify theA-state and the B-state, a second may be used to verify the C-state anda D-state, etc. In some cases, one or more initial program pulses arenot followed by verify pulses because it is not expected that anystorage elements have reached the lowest program state (e.g., A-state).Subsequently, program iterations may use verify pulses for the A-state,followed by program iterations which use verify pulses for the A- andB-states, followed by program iterations which use verify pulses for theB- and C-states, for instance.

FIG. 8 is a flowchart describing one embodiment of a programmingprocess, which includes one or more verification steps. In oneembodiment, the process is used to program memory cells on a selectedword line. In one embodiment, the process is used to program everymemory cell on the selected word line. In one embodiment, the process isused to program every other memory cell (e.g., odd/even programming) onthe selected word line.

In step 810, the program voltage (Vpgm) is set to an initial value. Inone embodiment, the magnitude of the program voltage depends on whichword line is selected for programming. In one embodiment, the initialmagnitude of Vpgm is lower when programming an edge word line. Also, instep 810, a program counter (PC) is initialized to zero.

In step 820, programming conditions are applied. One or more of theprogramming conditions may depend on the location of which word line isselected for programming. FIG. 9, to be discussed below, shows someexamples of programming conditions that may be applied during step 820.

Applying the programming conditions includes applying a programmingsignal (e.g., voltage pulse) to a selected word line. In one embodiment,the width of the voltage pulse depends on the location of the selectedword line on the NAND string. In one embodiment, the voltage pulse has ashorter width when an edge word line is selected for programming thanwhen one of the middle word lines is selected.

Step 820 may also include applying an appropriate voltage to bit lines.In one embodiment, a first voltage (e.g., a low voltage) is applied tobit lines associated with NAND strings having a memory cell presentlyundergoing normal (or fast) programming, a second voltage (e.g., amedium voltage) is applied to bit lines associated with NAND stringshaving a memory cell presently undergoing slow programming, and a thirdvoltage (e.g., a high voltage) is applied to bit lines associated withNAND strings having a memory cell presently inhibited from or locked outfrom further programming. In one embodiment, the magnitude of the firstvoltage depends on the location of the selected word line along the NANDstring. In one embodiment, the magnitude of the second voltage dependson the location of the selected word line along the NAND string. In oneembodiment, the magnitude of the third voltage depends on the locationof the selected word line along the NAND string.

Step 820 may also include applying an appropriate voltage to a commonsource line. In one embodiment, the magnitude of the voltage to a commonsource line depends on the location of the selected word line along theNAND string. Note that the common source line may be in electricalcontact with diffusion regions 431 of SGS transistors 406. Thus, in oneembodiment, the magnitude of the voltage applied to the (source)diffusion region 431 of an SGS transistor 406 depends on the location ofthe selected word line along the NAND string.

Step 820 may also include applying an appropriate voltage to a gate of aselect gate of a NAND string. Stated another way, step 820 may includeapplying an appropriate voltage to select line of a NAND string. Theselect gate may be for either a SGS transistor 406 or a SGD transistor424. Thus, the select line may be either a source side select line(e.g., SGS) or a drain side select line (e.g., SGD). In one embodiment,the magnitude of the voltage to the gate of a select transistor of aNAND string depends on the location of the selected word line along theNAND string. In other words, the magnitude of the voltage to a selectline (SGS and/or SGG) of a NAND string depends on the location of theselected word line along the NAND string.

Applying the program conditions in step 820 may also include applying apass voltage to unselected word lines. The magnitude of the pass voltagefor each unselected word line may depend on which boosting scheme isbeing used. A variety of boosting schemes including, but not limited to,self-boosting (SB), local self-boosting (LSB), and erase areaself-boosting (EASB) may be used. As is known to those of ordinary skillin the art, the magnitude of the pass voltage may be different fordifferent unselected word lines. Also, the magnitude of the pass voltagefor a given unselected word line may depend on the relative location ofthat unselected word line to the word line that is selected forprogramming. The pass voltage may help to reduce program disturb byboosting the voltage of the channel below the memory cell. Applyingprogramming conditions that depend on the location of the selected wordline may prevent or reduce leakage of the boosted channel potential.Therefore, program disturb may be prevented or reduced.

In step 822, a verification process is performed. In one embodiment, theverification is a concurrent coarse/fine verify. Referring to FIG. 7A,as one example, some memory cells that are being programmed to theA-state are verified using the VvaL level, and others that are beingprogrammed to the A-state are verified using the Vva level. During theinitial programming steps in which the memory cell's threshold is wellbelow the final level (Vva), course programming may be applied. However,after the memory cell's threshold voltage reaches VvaL, fine programmingmay be used. Thus, some memory cells are verified for coarseprogramming, whereas other memory cells are verified for fineprogramming. Note that when a particular memory cell has been verifiedas being programmed to its intended state, it may be locked out fromfurther programming. Note that using coarse/fine programming is notrequired. In one embodiment, the intermediate verify levels (e.g., VvaL,VvbL, etc.) are not used.

In step 824, it is determined whether all or almost all of the memorycells have verified that their threshold voltages are at the finaltarget voltage for that memory cell. If so, the programming process iscompleted successfully (status=pass) in step 826. If all or almost allof the memory cells are not verified to have reached their final targetlevels, then it is determined whether the program counter (PC) is lessthan a maximum value such as 20. If the program counter (PC) is not lessthan max (step 828), then the program process has failed (step 830). Ifthe program counter (PC) is less than a maximum value (e.g., 20), thenthe program counter (PC) is incremented by one and the program voltageis stepped up to the next pulse in step 832. Subsequent to step 832, theprocess loops back to step 820 and the next program pulse is applied tothe memory cells.

FIGS. 9(A)-9(H) are timing diagrams illustrating voltages during programoperations, according to one embodiment. The timing diagram depicts oneembodiment of programming conditions that are applied during step 820 ofprocess 800. In various embodiments, one or more of the programmingconditions depends on the location of the selected word line. In someembodiments, the magnitude of a voltage depends on the location of theselected word line. In one embodiment, the duration of the programvoltage depends on the location of the selected word line.

The voltages shown are applied to various select lines, word lines, bitlines, and the common source line of the memory array, for NAND stringsunder fast programming, slow programming, and program inhibition. Theprogram operation can be grouped into a Bit Lines Precharge Phase, aProgram Phase and a Discharge Phase.

Bit Lines Precharge Phase: During phase (1), the SGS transistors 406 areturned off by SGS being at Vsgs (FIG. 9(A)) while the SGD transistors424 are turned on by SGD going high to Vsg (FIG. 9(B)), thereby allowinga bit line to access a NAND string. In one embodiment, the magnitude ofVsgs depends on the location of the selected word line. In oneembodiment, the magnitude of Vsgs is higher when lower word lines arebeing programmed to prevent or reduce GIDL. In one embodiment, themagnitude of Vsgs is negative when middle word lines or higher wordlines are being programmed to prevent or reduce program disturbassociated with DIBL.

During phase (2), the bit line voltage of a program-inhibited NANDstring is allowed to rise to a predetermined voltage given byVBL_inhibit (FIG. 9(E)). When the bit line voltage of theprogram-inhibited NAND string rises to VBL_inhibit, theprogram-inhibited NAND string will float when the gate voltage on theSGD transistor 424 drops to V_SGD. In one embodiment, the voltageVBL_inhibit depends on which word line is selected for programming.

At the same time, the bit line voltage of a programming NAND string iseither pulled down to VBL_Select or maintained at VBL_Select if alreadythere (FIG. 9(G)). In one embodiment, the voltage VBL_Select depends onwhich word line is selected for programming.

Also during phase (2), the bit line voltage of NAND strings that areundergoing slow programming is set to an intermediate voltage given byVBL_QPW (FIG. 9(F)). The voltage VBL_QPW is between VBL_Select andVBL_inhibit. The voltage VBL_QPW allows the selected memory cell toprogram, but at a slower rate than if VBL_Select were used. In oneembodiment, the voltage VBL_QPW depends on which word line is selectedfor programming.

Also during phase (2), the voltage on the common source line is set tovoltage given by V_Cell_Source (FIG. 9(H)). In one embodiment, thevoltage V_Cell_Source depends on which word line is selected forprogramming.

During phase (3), the drain select line (SGD) connecting to the SGDtransistors 424 of NAND strings has its voltage lowered to V_SGD. In oneembodiment, this will float only those program-inhibited NAND stringswhere their bit line voltage is comparable to V_SGD, since their SGDtransistors 424 are turned off (FIGS. 9(B) & 9(E)). As for the NANDstrings containing a memory cell to be programmed, their SGD transistors424 will not be turned off relative to the bit line voltage (e.g., near0V) at their drain. In one embodiment, the voltage V_SGD depends onwhich word line is selected for programming.

In one embodiment, the voltage V_SGD depends on the location of theselected word line in order to prevent or eliminate effects of DIBL. Forexample, the SGD transistors 424 of unselected NAND strings may be keptoff despite their Vth being lowered by DIBL. In one embodiment, themagnitude of V_SGD is lower for higher selected word lines, which maykeep the SGD transistors 424 turned off despite possible DIBL.

In one embodiment, the magnitude of V_SGD depends on the location of theselected word line in order to prevent or eliminate effects of GIDL. Forexample, the magnitude of V_SGD may be higher when the selected wordline is near the SGD transistors 424 (relative to when the selected wordline is a middle word line, for example). This increase in V_SGD mayprevent leakage of charge from the boosted channel due to GIDL.

During phase (4), the memory cells in a NAND string not being programmedhave their control gate voltage set to VPASS (FIG. 9(C)). Also, thememory cell being programmed may have its control gate voltage set toVPASS (FIG. 9(D)). Since a program-inhibited NAND string is floating,the VPASS applied to the control gates of the memory cells boosts up thevoltages of their channels. For the sake of discussion, the entire NANDstring may be considered to have a channel. Thus, it may be stated thatVPASS boosts the channel voltage of the NAND string. VPASS may be set tosome intermediate voltage (e.g., ˜10V) relative to Vpgm (e.g., ˜15-24V).Depending on the boosting scheme being used, the value of VPASS is notrequired to be the same for each unselected word line.

Program Phase: During phase (5), a programming voltage Vpgm is appliedto the control gate of a memory cell selected for programming (FIG.9(D)). This may be achieved by applying Vpgm to the selected word line.The memory cells under program inhibition (e.g., with boosted channels)will not be programmed. The memory cells under programming will beprogrammed. Note that Vpgm may also contribute to channel boosting.Applying program conditions that depend on which word line is selectedmay prevent or substantially reduce the boosted channel voltage fromreducing during the program phase.

In one embodiment, the duration of the program pulse (e.g., duration ofphase 5) depends on the location of the selected word line. This mayhelp to reduce or eliminate program disturb.

In the Discharge Phase: During phase (6), the various control lines andbit lines are allowed to discharge.

Any combination of the selected word line dependent signals discussed inconnection with FIG. 9 may be used together when programmingnon-volatile storage.

Selected Word Line Dependent Programming Voltage Pulse Width

In one embodiment, the width (or duration) of a programming pulsedepends on the location of the word line that is selected forprogramming. As one example, a shorter width may be used whenprogramming edge word lines. Using a shorter width for the programmingpulse for edge word lines may reduce program disturb on those wordlines. If the programming pulse used for other word lines is too short,then a problem such as poor programming for the far end of the word linemay occur.

Each word line does not necessarily have the same physicalcharacteristics. For example, some word lines may be wider than others.As a specific example, edge word lines may be wider than other wordlines. A possible reason for this is due to limitations of thelithography process used to form the word lines. There may also bedifferences in doping profiles used in the substrate near edge wordlines compared to other word lines. Differences in physicalcharacteristics (not necessarily those physical characteristics justmentioned) may result in different optimum widths for programmingvoltages.

In one embodiment, the pulse width for each selected word line is suchthat Er-A failures are minimized, or at least close to the minimum. FIG.10 is a graph that shows Er-to-A failures versus program pulse width forselected word lines in various positions along a NAND string. Referringto FIG. 10, for any given word line there may be an optimum programpulse width to reduce Er-A failures. Curve 1001(1) is for edge wordlines, whereas curve 1001(2) is for middle word lines. As theprogramming pulse width is made shorter, the Er-A failures may bereduced up to a point. However, at some point, the Er-A failures maybecome greater as the program pulse width is further reduced. Also notethat the optimum pulse width for edge word lines may be shorter than formiddle word lines.

A possible reason for higher Er-A fails when the program pulse width istoo short is that a higher magnitude of program voltage may be needed tocomplete the programming of the word line. Needing to use a highermagnitude program voltage can increase program disturb, which countersthe beneficial effect of a shorter program pulse width.

In one embodiment, a program pulse width is determined for each wordline position based on how many program loops it takes to completeprogramming each word line. This may help to reduce failures due toproblems such as program disturb.

In one embodiment, the program pulse width depends on the selected wordline. In one embodiment, the program pulse width depends on the width ofthe selected word line. In one embodiment, a shorter program pulse widthis used for edge word lines. In one embodiment, a program pulse width isdetermined for each word line position based on the number of programloops it takes to complete programming each word line. Prior todiscussing various program processes in which the program pulse widthdepends on the selected word line, some word line dependentcharacteristics will be discussed.

FIGS. 11A, 11B, and 11C show example graphs of Vth distribution widthsversus program pulse widths. FIG. 11A is for the A-state, FIG. 11B isfor the B-state, and FIG. 11C is for the C-state. Each graph shows twoexample curves for edge word lines and two examples for “middle wordlines.” In FIG. 11A, 1101(a) is for the lowest edge word line, 1101(b)and 1101(c) are middle word lines, 1101(d) is the highest edge wordline. In FIG. 11B, 1102(a) is for the lowest edge word line, 1102(b) and1102(c) are for middle word lines, 1102(d) is for the highest edge wordline. In FIG. 11C, line 1103(a) is for the lowest edge word line,1103(b) and 1103(c) are for middle word lines, 1103(d) is for thehighest edge word line. The middle word lines may be about in themidpoint of the NAND string.

These graphs in FIGS. 11B and 11C show that the Vth distribution maybecome wider with shorter programming pulse width for all word lines, atleast for the B- and C-states. The Vth distribution width for theA-state might not depend on program pulse width as heavily as it doesfor other data states, although for some devices and programmingprocesses this may be a possibility.

Referring to FIGS. 11A-11C, the edge word lines may have a tighter Vthdistribution for a given pulse width than the middle word lines. Also,the “cliff” may occur at a lower program pulse width for the edge wordlines than for the middle word lines (see FIGS. 11B and 11C). The cliffrefers to the point at which the Vth distribution widening begins toincrease rapidly with shorter program pulse width. Since the cliff maybe lower for the edge word lines (at least for some data states), theedge word lines may be more tolerant to shorter program pulse widths.

FIG. 12 shows a graph of program loop count versus program pulse width.The graph shows two curves for edge word lines (1201(a), 1201(f)) andfour curves for middle word lines (1201(b), 1201(c), 1201(d), 1201(e)).These edge word lines may be WL0 and WL63, as one example. However,there may be more or fewer word lines. The middle word lines may be WL1,WL32, WL33, and WL62. Thus, in this example, there is one edge word lineat each end of the NAND string. As noted earlier, in some contexts theremay be more than one edge word line at each and of the NAND string. Thenumber of program loops may increase with decreasing program pulsewidth. Note that the edge word lines may program faster than the middleword lines across all program pulse widths. In one embodiment, toachieve the same program loop (program performance) for edge WLs andmiddle WLs, a shorter program pulse width may be used on edge WLs.

FIGS. 13A and 13B are graphs that show word lines RC dependence. FIG.13A is for a relatively long program pulse width. FIG. 13B is for arelatively moderate program pulse width. Curves 1301(a) and 1301(b) arefor edge word lines. Curves 1301(c) and 1301(d) are for middle wordlines. Each curve 1301(a)-1301(d) shows the average Vth of memory cellsat different points along the selected word line. In this example, eachword line may be programmed pulse by pulse without verify. The memorycells may be grouped into segments, based on physical location. Forexample, memory cells may be grouped into 72 segments (segments 0-71)for purposes of analysis. The Vth for each memory cell in a givensegment may be averaged to produce an average Vth for that segment. TheVth difference between segment 0 and segment 71 may be a measure of RCdelay along the word line.

Note that when the program pulse width is shorter (FIG. 13B), the middleword lines 1301(c), 1301(d) show a significant drop in Vth for thehigher segments. This may be due to significant RC delay whenprogramming the middle word lines. However, the edge word lines 1301(a),1301(b) do not show as much of a drop in Vth for higher segments. Thismay be due to there being less RC delay for edge word lines. Word linewidth may affect RC delay. As one example, edge word lines may be wider,thus having less RC delay. For some devices, even word lines and oddword lines have different widths. Therefore, even and odd word lines mayhave different RC delay.

Referring now to FIG. 13A, neither the edge 1301(a), 1301(b) nor themiddle word lines 1301(c), 1301(d) show as much of a drop in Vth for thehigher segments. As noted, the program pulse width is longer in thiscase. Therefore, the RC delay along the word line may not be asimportant since the pulse width is longer.

Characteristics of the lithographic process used to form the word linesmay determine the width of word lines. For example, the intent may be toform all word lines with the same width, edge word lines may end upwider than middle word lines. A possible reason for this is that theedge word lines are near select lines, which may be intended to besignificantly wider than word lines. For some lithographic processeswhen parallel lines are formed, the process may work best if the linesare of the same width. However, since an edge word line is locatedbetween relatively narrow middle word lines and a relatively wideselected line, the edge word line may end up larger than middle wordlines.

In view of the difference in RC delay for different word lines,programming in accordance with one embodiment uses shorter program pulsewidths for word lines having less RC delay. In one embodiment, edge wordlines have less RC delay than middle word lines. For some devices, theword lines with less RC delay may be otherwise. One factor in havingless RC delay may be the width of word lines. However, there may beother factors.

FIG. 14 is a flowchart of one embodiment of a process 1400 ofprogramming non-volatile storage. In step 1402, a programming voltage isapplied to a selected word line that has a duration that depends on thewidth of the selected word line. The duration of the program voltage maybe defined as a program voltage pulse width. Process 1400 may be used toimplement a portion of step 820 from FIG. 8. Specifically, applying aprogram voltage to a selected word line is one of the program conditionsof step 820. Referring to FIG. 9(D), step 1402 is one embodiment ofapplying Vpgm during the program phase. Thus, the time duration of phase(5) depends on the selected word line, in one embodiment. Various othersignals depicted in FIG. 9 may also be applied during process 1400. Zeroor more of these signals may have its value depend on the selected wordline.

Step 820 may be performed multiple times to program the selected wordline. In one embodiment, the same program pulse width is used for eachprogram loop when programming the selected word line. However, theprogram pulse width could be changed with the number of program loops.

In one embodiment, a shorter pulse width is used in step 1402 for widerword lines (and wider for more narrow word lines). In one embodiment,edge word lines are wider than middle word lines. Thus, a shorterprogram pulse width may be used for edge word lines than for middle wordlines.

FIG. 15 is a flowchart of one embodiment of a process 1500 ofprogramming non-volatile storage. Process 1500 describes programming alowest word line, a middle word line, and a highest word line. By alowest word line, it is meant the lowest word line for which user orsystem data is stored. There may also be one or more dummy word lines inbetween the lowest word line and the source side select line. Likewise,by a highest word line, it is meant the highest word line for which useror system data is stored. There may also be one or more dummy word linesin between the highest word line and the drain side select line. Thelowest and highest word lines may be referred to as “edge” word lines.For memory devices in which the edge word lines are wider than themiddle word lines, process 1500 is one implementation of step 1402 fromprocess 1400.

Process 1500 describes programming signals that are applied to threedifferent word lines for the same point in the programming process whendifferent word lines are selected for programming. As noted, theprogramming process has a number of program loops (or steps). By thesame point it is meant the loop (or program step). This could be theinitial program loop or some other program loop.

In step 1502, a programming signal having a first pulse width is appliedto a lowest word line. Referring to FIG. 2, this may be applied to WL0.Referring to FIG. 3, this may be applied to WL0. Referring to FIG. 5A,this may be applied to WL0. Step 1502 is one embodiment of step 820 fromprocess 800. In one embodiment, step 1502 is for the first program pulsethat is applied to the lowest word line (e.g., first iteration ofprocess 800). Referring to FIG. 9(D), step 1502 is one embodiment ofapplying Vpgm during the program phase.

There is a dashed line between step 1502 and 1504 to indicate that otherprogramming signals may be applied to the lowest word line to completeits programing before proceeding on to program the middle word line. Instep 1504, a programming signal having a second pulse width is appliedto a middle word line. In one embodiment, the programming signal isapplied to any word line between the lowest and highest word lines.However, there may be more than one edge word line at each end of thestring of memory cells (e.g., NAND string). For example, there might betwo or three edge word lines at each end. Thus, the middle word line isnot necessarily any word line between the lowest and highest word lines.The second pulse width is longer than the first pulse width. In oneembodiment, step 1504 is for the first program pulse that is applied tothe middle word line (e.g., first iteration of process 800). Referringto FIG. 9(D), step 1504 is one embodiment of applying Vpgm during theprogram phase.

In step 1506, a programming signal having a third pulse width is appliedto a “highest” word line. Again, the dashed line between steps 1504 and1506 indicates that other programming signals may be applied to themiddle word line to complete its programming prior to going on toprogram the highest word line. Also, note that numerous middle wordlines may be programmed. The highest word line may be the word line thatis closest to the SGD transistor 424, and that is used to store user orsystem data. Referring to FIG. 2, this may be applied to WL3. Referringto FIG. 3, this may be applied to WL7. Referring to FIG. 5A, this may beapplied to WL63. The third pulse width is shorter than the second pulsewidth. The third pulse width may be the same, shorter than, or longerthan the first pulse width. In one embodiment, step 1306 is for thefirst program pulse that is applied to the highest word line (e.g.,first iteration of process 800). Referring to FIG. 9(D), step 1506 isone embodiment of applying Vpgm during the program phase. Various othersignals depicted in FIG. 9 may also be applied during process 1500. Zeroor more of these signals may have its value depend on the selected wordline.

Thus, in one embodiment, process 1500 includes applying a programmingsignal for a given program loop having a shorter pulse width when eitherthe lowest word line or the highest word line is selected forprogramming than the pulse width used to program at least one other wordline of the plurality of word lines.

For some devices, the lowest word line and the highest word line may bewider than middle word lines. In this case, process 1500 may be used toimplement step 1402. In other words, process 1500 may result in applyinga program voltage whose duration depends on the width of the selectedword line. One possible reason for the edge word lines being wider thanothers is due to the lithographic process used to form the word lines.For some devices, the select lines (e.g., SGD and SGS in FIG. 5A) arewider than the word lines. For some lithographic processes, this mayresult in edge word lines printing somewhat wider than other word lines.Note that for other lithographic processes other word lines could bewider.

FIG. 16 is a flowchart of one embodiment of a process 1600 ofprogramming non-volatile storage that involves determining a width of aprogram pulse. Referring to FIG. 9, process 1600 may be used todetermine the time duration of the program phase.

In step 1602, a width of a program pulse for the selected word line isdetermined. In one embodiment, this determination is made by accessing atable. FIG. 17 shows details of one embodiment of a process 1700 fordetermining a width for a particular word line. Process 1700 may be usedto create the table accessed in step 1602.

In step 1604, a programming signal with the width (or time duration)determined in step 1602 is applied to the selected word line. Step 1604may be repeated until all memory cells on the selected word line areprogrammed. Various other signals depicted in FIG. 9 may also be appliedduring process 1600. Zero or more of these signals may have its valuedepend on the selected word line.

If there are more word lines to program, then process 1600 returns tostep 1402. In one embodiment, word lines in a block are programmingsequentially from lowest to highest. However, word lines may beprogrammed in any order.

FIG. 17 is a flowchart of a process 1700 of determining suitable pulsewidths for programming signals for word lines, depending on theirposition. The process 1700 may be performed on a sample block, with theresults being used to program other blocks. The sample block may be inthe same storage device as the other blocks, but this is not required.Some storage devices have more than one memory die. In this case, thesample block may be on the same memory die or another memory die.

In step 1702, each word line in the sample block is programmed. Aprocess such as the one in FIG. 8 may be used to program each word line.In one embodiment, the starting voltage (Vpgm) may be the same for eachword line. As one example, for the first program loop, the pulse 752depicted in FIG. 7B may be applied separately to each word lines when itis the word line selected for programming. For the second program loop,the pulse 754 may be applied. Pulse 756 may be applied for the thirdloop, pulse 758 for the fourth loop. For additional loops, the pulsemagnitude may be increased further. This allows for each word line toreceive the same programming voltage (magnitude and duration) for eachprogram loop. Note that the same pulse width may be used such that eachword line receives similar programming voltages. Also note that it isnot required to use the sequence of pulses as depicted in FIG. 7B. Forexample, the voltage magnitude is not required to increase with eachprogram loop.

In step 1704, the number of program loops that it took to completeprogramming each word line is determined. Referring back to FIG. 8,recall that the program voltage may be incremented with each loop(although increasing Vpgm each loop is not required). Thus, onealternative is to determine the final program voltage for each wordline. Stated another way, for some programming processes, determiningthe final program voltage may be the equivalent of determining thenumber of program loops.

In step 1706, a pulse width pattern for programming word lines in otherblocks is determined. By a pulse width pattern it is meant a pulse widthfor a word line selected for programming at each position. For example,a table may be constructed with an entry for each word line and asuitable pulse width. However, it is not required that the table has aunique entry for each word line. In one embodiment, word lines aregrouped into zones, with each word line in the zone having the samepulse width. These zones may be physically contiguous word lines. Anynumber of zones may be used. One zone may have a different number ofword lines than another zone. In one embodiment, the table has a zonefor edge word lines and a zone for all middle word lines. In oneembodiment, the table has one zone for edge word lines near the SGStransistor 406 and one zone for edge word lines near the SGD transistor424 (and one or more zones for middle word lines). In one embodiment,the table formed is process 1700 is used in step 1602 of FIG. 16.

Selected Word Line Dependent Select Gate Diffusion Region Voltage

One problem that may occur when programming NAND strings is leakage ofcurrent from a boosted channel. This current leakage can reduce theboosted channel potential of inhibited NAND strings. Therefore, programdisturb may occur. FIG. 18A shows a NAND string that is inhibited fromprogramming. A voltage V_BL_Inhibit is applied to the bit line contact426. A boosting voltage Vpass is applied to control gates of unselectedmemory cells. A program voltage Vpgm is applied to the control gate ofthe selected memory cell. V_(SGS) and V_(SGD) are applied to the SGStransistor 406 and the SGD transistor 424, respectively. In thisexample, a voltage Vgp is applied to gates of dummy memory cells. Thisvoltage may help to reduce GIDL. Note that neither the dummy memorycells, nor applying Vgp to the dummy memory cells is a requirement.However, even if a voltage Vgp is applied to the dummy memory cells,there still may be GIDL, as discussed below.

FIG. 18A shows a boosted NAND string having SGS leakage current and SGDleakage current. FIG. 18A shows an SGS leakage current that may occuracross the channel of the SGS transistor 406, and an SGD leakage currentthat may occur across the channel of the SGD transistor 424. Thisleakage current may be due, at least in part, to punch-throughconduction. One factor in this leakage current is the magnitude of theboosted channel potential relative to the source 431 or drain 432 of theselect transistors 406, 424. For example, for SGS transistor 406, theboosted channel potential may be a higher voltage than the voltageapplied to the source line contact 404. Also, the boosted channelpotential may be higher than the bit line voltage, Vbl_inhibit, that isapplied to bit line contact 426.

Another possible factor in current leakage is the channel length of theSGS and SGD transistors 406, 424. As memory devices continue to scaledown, it is desirable to reduce the length of the gate of the SGS andSGD transistors 406, 424. However, reducing the length of the gate canincrease the leakage current for inhibited NAND strings duringprogramming. As noted, one factor in the increased leakage current maybe punch-through conduction.

In one embodiment, the magnitude of the voltage that is applied to aterminal of an SGS or SGD select transistor 406, 424 of a NAND stringdepends on the location of the word line that is selected forprogramming. In one embodiment, the terminal is either a source 431 or adrain 432. In one embodiment, the magnitude of the voltage applied tothe bit line depends on the location of the word line selected forprogramming. The bit line may be in electrical contact with the drain432 of an SGD transistor 424. In one embodiment, the magnitude of thevoltage applied to the common source line depends on the location of theword line selected for programming. The common source line may be inelectrical contact with the sources 431 of SGS transistors 406 of NANDstrings.

Applying a selected word line dependent voltage to a source 431 or drain432 of, respectively, an SGS or SGD select transistor 406, 424 mayreduce or eliminate punch-through current leakage. For example, this mayeliminate current from leaking from a boosted channel of a NAND stringacross the channel of an SGS or SGD select transistor 406, 424 at theend of the NAND string. Reducing or eliminating the punch-throughleakage helps to keep the channel potential boosted. Therefore, programdisturb may be reduced or eliminated.

FIG. 19 is a flowchart of a process 1900 of one embodiment ofprogramming non-volatile storage that may counteract punch-throughleakage. In process 1900 the magnitude of the voltage that is applied toa diffusion region 431, 432 of at least one of the select transistors406, 424, depends on the location of the selected word line. Process1900 may reduce or eliminate punch-through conduction, which may reduceor eliminate program disturb. Process 1900 may be used to program memorycells of NAND strings each having a first select transistor at a firstend and a second select transistor at a second end. Process 1900 is oneembodiment of applying program conditions as indicated in step 820 ofprocess 800.

In step 1902, voltage is applied to a diffusion region 431, 432 of aselect transistor 406, 424 of at least one of the NAND strings. Notethat the diffusion region 431, 432 is on the opposite of the selecttransistor 406, 406 as the NAND string channel. The magnitude of thevoltage applied to the diffusion region 431, 432 depends on the locationof a selected word line on the NAND strings. In one embodiment, thevoltage is applied to a contact to a NAND string. The contact may be abitline contact 426 or a source line contact 404. When applied to abitline, the voltage is applied to bitlines associated with NAND stringsthat are not selected for programming, in one embodiment. In oneembodiment, the voltage is first applied during a bit line pre-chargeand boosting phase (see FIG. 9). In one embodiment, the voltagecontinues to be applied during a program phase.

In one embodiment, the voltage is applied to the bit line (or bit linecontact 426) associated with inhibited (or unselected) NAND strings.Stated another way, the voltage is applied to the (drain) diffusionregion 432 of SGD transistors 424 of inhibited NAND string. Referring toFIG. 9(E), the value of VBL_inhibit is selected based on which word lineis being programmed, in one embodiment of step 1902.

In one embodiment of step 1902, the voltage is applied to the (source)diffusion region 431 of an SGS transistor 406. In one embodiment, thevoltage is applied to the common source line (or source contact 404)associated with the NAND strings. Referring to FIG. 9(H), the value ofVcell_src is selected based on which word line is being programmed, inone embodiment of step 1902.

In step 1904, a program voltage is applied to the selected word linewhile applying the voltage to the diffusion region of the selecttransistor 406, 424. Referring to FIG. 9(D), Vpgm may be applied to theselected word line during the program phase.

FIG. 20A shows relative values for Vcel_src versus word lines inaccordance with one embodiment. As noted, Vcel_src may be applied to thecommon source line during a program operation (see FIG. 9(H), forexample). In this embodiment, word lines are divided into three zones.In general, there may be two or more zones. In this embodiment, Vcel_srchas the highest magnitude for the lowest word lines (e.g., WL0 toWLx−1). There may be one or more word lines in this first zone. In thisembodiment, Vcel_src has a medium magnitude for the middle word lines(e.g., WLx to WLy−1). There may be one or more word lines in this secondzone. In this embodiment, Vcel_src has the lowest magnitude for thehighest word lines (e.g., WLy to the highest WL). There may be one ormore word lines in this third zone.

Referring again to FIG. 18A, using a higher voltage for Vcel_src for thelowest word lines may reduce SGS leakage current. Recall that FIG. 18Ais for an inhibited NAND string with a boosted channel. Typically,Vcel_src is lower in magnitude than the channel potential of a boostedNAND string. Therefore, there may be a significant voltage from NANDchannel to the diffusion region 431 of the SGS transistor 406. Thus,there may be a significant voltage across the channel of the SGStransistor 406. Stated another way, there is a significant Vds voltagefor the SGS transistor 406. Consequently, there may be a significantE-field across the channel of the SGS transistor 406.

Increasing the magnitude of Vcel_src reduces this Vds voltage for theSGS transistor 406. In other words, the E-field across the SGStransistor 406 may be reduced. Consequently, the SGS leakage current maybe reduced. In turn, this means that the channel boosting may beimproved. For example, the voltage of the boosted channel may be bettermaintained because the SGS leakage current may be reduced. Therefore,program disturb may be reduced or eliminated.

However, increasing the magnitude of Vcel_src may itself cause problems.One possible problem is the risk of junction stress for the source linecontact which may cause undesired junction leakage. Another undesiredleakage path may occur during programming. NAND strings that have amemory cell currently being programmed may have a channel voltage ofabout 0V, or some other voltage that is significantly lower than theboosted channel voltage of inhibited NAND strings. If the value ofVcel_src is allowed to go too high, then there could possibly be somecurrent leakage from the common source line into the channels of NANDstrings undergoing programming. This current leakage could besignificant and may lead to undesirable power consumption.

Another factor to consider is that the magnitude of the boosted channelvoltage may depend on which word line is being programmed. For example,the channel may boost to a higher potential when lower word lines areselected. In one embodiment, word lines are programmed in general fromlowest word line to highest (note that it is not required to strictlyfollow this sequence). Thus, when the lower word lines are beingprogrammed, drain side memory cells are still in the erase state. Amemory cell that is erased may be more effective at boosting the channelvoltage than a memory cell that is programmed to a higher data state.

Thus, when the lowest word lines are being programmed, the channel mightboost to a higher voltage. This higher channel voltage could result inpunch through conduction of the SGS transistor 406, if the value ofVcel_src were not increased. However, the embodiment depicted in FIG.20A uses a higher Vcel_src when programming lower word lines. Therefore,SGS leakage current may be reduced or eliminated.

However, the embodiment depicted in FIG. 20A uses a lower Vcel_src whenprogramming the highest word lines. For some boosting schemes, thechannel voltage might not be that high (at least at the source end) whenprogramming the highest word lines. Therefore, the value of Vcel_src maynot need to be raised for this case to prevent punch through conductionat the SGS transistor 406. By not using a higher Vcel_src, the risk ofcurrent leaking from the common source line to the channels of selectedNAND strings may be avoided.

The embodiment depicted in FIG. 20A also shows a middle zone for wordlines in the middle. There may be word lines in the middle for which theamount of channel boosting (at least at the source end) is not quite ashigh as the case for the lowest word lines, but high enough such thatSGS leakage current is a significant problem. For these middle wordlines, using the middle value for Vcel_src may reduce or eliminate SGSleakage current, while putting less stress on the source contactjunction. Thus, less (or no) current leaks from the common source lineto the channels of selected NAND strings.

As noted above, there may be any number of zones of different values forVcel_src. In one embodiment, the value of Vcel_src decreases for zoneshaving higher word lines.

FIG. 20B depicts a flowchart of one embodiment of a process 2000 ofprogramming non-volatile storage. Process 2000 is one embodiment ofprocess 1900. In step 2002, a voltage that depends on the location ofthe word line that is selected for programming is applied to the commonsource line. Referring to FIG. 9(H), the value of Vcell_src is selectedbased on the location of the word line being programmed, in oneembodiment.

In one embodiment, step 2002 includes applying a first voltage to asource line contact 404 if the selected word line is in a first group ofone or more word lines, and applying a second voltage to the source linecontact 404 if the selected word line is in a second group of the wordlines. Referring to FIG. 20A, the first group of word lines (e.g., WL0to WLx−1) is closer to the SGS transistor 406 than the second group ofword lines (e.g., WLx to WLy−1 or WLy to the highest word line), in oneembodiment. The first voltage (e.g., Vcel_src_(—)1) is greater than thesecond voltage (e.g., Vcel_src_(—)2 or Vcel_src_(—)3), in oneembodiment.

In step 2004, a program voltage is applied to the selected word linewhile applying the voltage to the common source line. Referring to FIG.9(D), the voltage Vpgm may be applied to the select word line during theprogram phase. Various other signals depicted in FIG. 9 may also beapplied during process 2000. Zero or more of these signals may have itsvalue depend on the location of the selected word line.

In one embodiment, the voltage applied to bit lines associated with NANDstrings that are not selected for programming depends on the location ofthe selected word line. FIG. 21A shows relative values for Vbl_inhibitversus word lines in accordance with one embodiment. Vbl_inhibit may beapplied to the bit line of unselected NAND strings during a programoperation (see FIG. 9(E), for example). In this embodiment, word linesare divided into three zones. In general, there may be two or morezones. In this embodiment, Vbl_inhibit has the highest magnitude for thelowest word lines (e.g., WL0 to WLm−1). There may be one or more wordlines in this first zone. In this embodiment, Vbl_inhibit has a mediummagnitude for the middle word lines (e.g., WLm to WLn−1). There may beone or more word lines in this second zone. In this embodiment,Vbl_inhibit has the lowest magnitude for the highest word lines (e.g.,WLn to the highest WL). There may be one or more word lines in thisthird zone.

Referring again to FIG. 18A, typically, Vbl_inhibit is lower inmagnitude than the channel potential of a boosted NAND string.Therefore, there may be a significant voltage across the channel of theSGD transistor 424. Stated another way, there may be a significantvoltage between the NAND channel near the SGD transistor 424 and thediffusion region 432. Therefore, there is a significant Vds for the SGDtransistor 424. Note that since the boosted NAND channel voltage may begreater than Vbl_inhibit, the diffusion region 432 could be consideredto be the source side of the SGD transistor 424 in this context. As aresult of the Vds, may be a significant E-field across the channel ofthe SGD transistor 424. This E-field may lead to SGD leakage currentfrom the NAND channel to the diffusion region 432.

Increasing the magnitude of Vbl_inhibit may reduce Vds of the SGDtransistor 424. In other words, the E-field across the channel of theSGD transistor 424 may be reduced. Consequently, the SGD leakage currentmay be reduced. In turn, this means that the channel boosting may beimproved. For example, the voltage of the boosted channel may be bettermaintained because the SGD leakage current may be reduced. Therefore,program disturb may be reduced or eliminated.

However, increasing the magnitude of Vbl_inhibit may itself causeproblems. One possible problem is the risk of junction stress for thebit line contact which may cause increased junction leakage. Anotherundesired effect of using a higher Vbl_inhibit is increased powerconsumption during the precharging of the bitlines at the beginning ofthe programming. As the bitline-to-bitline capacitance is notnegligible, a significant amount of power may be consumed duringprecharging; therefore, as low as possible Vbl_inhibit may be desired.

As previously discussed, when the lowest word lines are beingprogrammed, the channel might boost to a higher voltage. This higherchannel voltage could result in SGD leakage, if the value of Vbl_inhibitwere low enough to allow punch through conduction. However, theembodiment depicted in FIG. 21A uses a higher Vbl_inhibit for the lowerword lines. Therefore, SGD leakage may be reduced. Note that if punchthrough conduction is a problem with middle or upper word lines, then ahigher Vbl_inhibit could be used when those word lines are programmed.

On the other hand, the embodiment depicted in FIG. 21A uses a lowerVbl_inhibit for the highest word lines. For some boosting schemes, thechannel voltage might not be that high (at least at the drain end) whenprogramming the highest word lines. Therefore, the value of Vbl_inhibitdoes not need to be raised for this case to avoid punch throughconduction.

The embodiment depicted in FIG. 21A also shows a middle zone for wordlines in the middle. There may be word lines in the middle for which theamount of channel boosting (at least at the drain end) is not quite ashigh as the case for the lowest word lines, but high enough such thatSGD leakage is a significant problem. For these middle word lines, usingthe middle value for Vbl_inhibit reduces or eliminated SGD leakage,while putting less stress on the bit line contact junction and alsoreducing power consumption during precharging.

As noted above, there may be any number of zones of different values forVbl_inhibit. In one embodiment, the value of Vbl_inhibit decreases forzones having higher word lines.

FIG. 21B shows relative values for Vbl_inhibit versus word lines inaccordance with one embodiment. Vbl_inhibit may be applied to the bitline of unselected NAND strings during a program operation (see FIG.9(E), for example). In this embodiment, word lines are divided into twozones. In general, there may be two or more zones. In this embodiment,Vbl_inhibit has the highest magnitude (Vbl_inhibit_B) for the highestword lines (e.g., WLp to the highest word line). There may be one ormore word lines in this zone. In this embodiment, Vbl_inhibit has lowermagnitude (Vbl_inhibit_A) for at least some of the word lines belowthis. In this example, all word lines between WL0 and WLp−1 have thevoltage (Vbl_inhibit_A). However, a scheme such as depicted in FIG. 21Amight be used for these lower word lines. FIG. 21C shows one suchexample.

FIG. 21D shows an inhibited NAND string with a boosting scheme referredto as Erase Area Self Boosting (EASB). FIG. 21D depicts across-sectional view of an unselected NAND string showing programmed anderased areas with erased area self-boosting (EASB). The view issimplified and not to scale. During programming, V_(PGM) is provided ona selected word line, in this case, WL5, which is associated with aselected storage element 418.

In one example boosting scheme, when storage element 418 is the selectedstorage element, a relatively low voltage, V_(LOW), e.g., 4 V, isapplied to a neighboring source-side word line (WL3), while an isolationvoltage, V_(ISO), e.g., 0-2.5 V, is applied to another source-side wordline (WL2), referred to as an isolation word line and V_(PASS) isapplied to the remaining word lines associated with NAND string 400(i.e., WL0, WL1, WL4, WL6 and WL7). V_(SGS) is applied to the selectgate 406 and V_(SGD) is applied to the select gate 424.

Assuming programming of storage elements along the NAND string 400progresses from storage element 408 to storage element 422, when storageelements associated with WL5 in other NAND strings are being programmed,storage elements 408-416 will already have been programmed, and storageelements 420 and 422 will not yet have been programmed. Note thatstorage element 418 is not programmed when the NAND string 400 isinhibited, in this example, even though a program voltage is applied onWL5. Thus, all or some of storage elements 408-416 will have electronsprogrammed into and stored in their respective floating gates, andstorage elements 420 and 422 can be erased or partially programmed,depending on the programming mode. For example, the storage elements 420and 422 may be partially programmed when they have been previouslyprogrammed in the first step of a two-step programming technique.

With the EASB boosting mode, V_(ISO) is applied to one or moresource-side neighbors of the selected word line and is sufficiently lowto isolate programmed and erased channel areas in the substrate, at somepoint after boosting is initiated. That is, a channel area 450 of thesubstrate on a source-side of the unselected NAND string 400 is isolatedfrom a channel area 460 on a drain-side of the unselected NAND string400. The source side can also be considered to be a programmed sidesince most or all of the associated storage elements have beenprogrammed, while the drain side can also be considered to be anunprogrammed side since the associated storage elements have not yetbeen programmed. Further, the channel area 450 is a first boosted regionof the substrate 490 which is boosted by the application of V_(PASS) onWL0 and WL1, while the channel area 460 is a second boosted region ofthe substrate 490 which is boosted mainly by the application of V_(PGM)on WL5 and V_(PASS) on WL4, WL6 and WL7. Since V_(PGM) dominates andalso because precharging is more efficient for erased memory cells, theerased area 460 will experience relatively higher boosting than theprogrammed area 450. Moreover, the channel boosting may be provided fora time period before V_(PGM) is applied, at which time the channel areas450 and 460 are similarly boosted.

As programming progresses to the highest word lines, the erased area ofthe channel 460 will consist of fewer memory cells having Vpass appliedto their gates. However, there will always be one with Vpgm applied.Since Vpgm is a higher voltage than Vpass, the average voltage appliedto the gates of memory cells in the erased area may increase as higherword lines are programmed. This may increase the boosted channelpotential. It is possible that the channel can boost up to asufficiently high voltage such that punch through conduction occurs(e.g., SGD leakage).

Referring again to FIG. 21B, in one embodiment, the bit line voltage forinhibited NAND strings is increased with higher word lines. This mayprevent or reduce punch through conduction. This may be used when EASBis used, but may also be used for other boosting modes.

FIG. 21E depicts a flowchart of one embodiment of a process 2100 ofprogramming non-volatile storage in which a bit line voltage depends onthe selected word line. Process 2100 is one embodiment of process 1900.In step 2102, a voltage is applied to bit lines of unselected NANDstrings. The voltage depends on the location of the word line that isselected for programming. Referring to FIG. 9(E), the voltageVBL_inhibit may be applied. In one embodiment, this is first appliedduring a bit line pre-charge and boosting phase. The voltage may bemaintained during a program phase.

In one embodiment, step 2102 includes applying a first voltage to a bitline contact 426 if the selected word line is in a first group of one ormore word lines, and applying a second voltage to the bit line contact426 if the selected word line is in a second group of the word lines.Referring to FIG. 21A, the first group of word lines (e.g., WL0-WLm−1))is closer to the SGS transistor 406 than the second group of word lines(e.g., WLm to WLn−1 or WLn to the highest word line), in one embodiment.The first voltage (e.g., Vbl_inhibit_(—)1) is greater than the secondvoltage (e.g., Vbl_inhibit_(—)2 or Vbl_inhibit_(—)3), in one embodiment.

In one embodiment, step 2102 includes applying a first voltage to bitlines of unselected NAND strings if the selected word line is in a firstgroup of one or more word lines, and applying a second voltage to thebit lines of the unselected NAND strings if the selected word line is ina second group of one or more word lines. In this embodiment, the firstgroup is closer to the SGD transistor 424, and the first voltage isgreater in magnitude than the second voltage. Referring to FIG. 21B, thefirst group of word lines (e.g., WLp to the highest word line) is closerto the drain select transistor 424 than the second group of word lines(e.g., WL0 to WLp−1), in one embodiment. The first voltage (e.g.,Vbl_inhibit_B) is greater than the second voltage (e.g., Vbl_inhibit_A),in one embodiment.

In step 2104, a program voltage is applied to the selected word linewhile applying the voltage to the bit lines of unselected NAND strings.Referring to FIG. 9(D), the voltage Vpgm may be applied.

Various other signals depicted in FIG. 9 may also be applied duringprocess 2100. Zero or more of these signals may have its value depend onthe selected word line. In one embodiment, step 2102 of process 2100 isperformed together with step 2002 of process 2000. Thus, the magnitudeof the voltage applied to both the common source line and the bit linesassociated with unselected NAND strings depend on the location of theword line selected for programming, in one embodiment.

GIDL Protect

Another possible problem that may occur to inhibited NAND strings duringprogramming is GIDL. Referring now to FIG. 18B, GIDL may occur due torelatively low voltage to the gate of a SGS transistor 406. FIG. 18Bshows a portion of the NAND string near the SGS transistor 406.Electrons may be generated in roughly the area depicted by the dashedregion labeled “GIDL.” There may be an Electric Field in which theelectrons may be accelerated towards the channels of the memory cells.Some of these electrons may be injected into a floating gate of a memorycell that has a program voltage applied to its control gate via hotcarrier injection. In some cases, electron injection in the floatinggate of a memory cell may occur even when a relatively low voltage, suchas Vpass, is applied to its control gate. These additional electrons mayincrease the Vth of the memory cell further than desired, thus creatingprogram disturb. Note that this problem could affect memory cells thathave been programmed to any data state, as well as those intended tostay erased.

As mentioned above, a GIDL protect voltage Vgp may be applied to thegate of a dummy memory cell. This voltage could be somewhat less thanVpass. Using a lower voltage than Vpass to the dummy may reduce theE-field both close to the SGS transistor and in the channel area inbetween SGS and the word lines, which may reduce both GIDL and thelateral electric field that is responsible for creating the hotelectrons. However, this may not entirely eliminate GIDL or the GIDLinduced hot electron injection. It is not required that there be a dummymemory cell 407 or that Vgp be applied to the memory cell closest to theselect transistor.

In one embodiment, the voltage that is applied to the gate of the SGStransistor 406 during programming depends on the position of theselected word line. This may help to reduce or eliminate program disturbdue to GIDL. For some programming schemes, GIDL induced program disturbfor the SGS transistor 406 may be most problematic for lower word lines.In one embodiment, VSGS is increased when programming lower word linesto reduce GIDL. Therefore, GIDL induced hot electron injection may bereduced or eliminated for the lower word lines. Consequently, programdisturb is reduced or eliminated.

GIDL may also be a problem on the drain side of the NAND string, asdepicted in FIG. 18C. Referring now to FIG. 18C, GIDL may occur due torelatively low voltage to the gate of an SGD transistor 424. FIG. 18Cshows a portion of the NAND string near the SGD transistor 424. In oneembodiment, the voltage that is applied to the gate of the SGDtransistor 424 during programming depends on the position of theselected word line. In one embodiment, VSGD is increased whenprogramming the highest word lines (relative to those just below this)to reduce GIDL. This may help to reduce or eliminate program disturb dueto GIDL at the drain side.

FIG. 22A depicts a flowchart of one embodiment of a process 2200 ofprogramming non-volatile storage. Process 2200 is one embodiment of step820 of process 800. In step 2202, a voltage is applied to a gate of anSGS transistor 406. The voltage depends on the location of the word linethat is selected for programming. Referring to FIG. 9(A), the magnitudeof the voltage SGS depends on the selected word line in one embodiment.In one embodiment, SGS is held at this voltage during both a bit linepre-charge (and boosting) phase and a program phase.

In one embodiment, Vsgs might be raised about 0.5V to prevent or reduceeffects of GIDL. Vsgs could be raised by more or less than 0.5V toprevent or reduce effects of GIDL. Referring to FIG. 22B, for edge wordlines from WL0 to WLp−1, Vsgs_(—)1 is higher than Vsgs_(—)2 for higherword lines (WLp to the highest word line). There may be one or more ofthe edge word lines near the SGS transistor 406 for which the highervoltage is applied to prevent or reduce effects of GIDL.

In some embodiments, Vsgs does not have the same value for all of thehigher word lines. In such embodiments, the value of Vsgs for the edgeword line(s) near the SGS transistor 406 is higher than the value ofVsgs for the lowest middle word line. For example, Vsgs is higher forWL0 than for WL1, such that effects of GIDL are reduced or prevented.

In one embodiment of step 2202, one of a plurality of different voltagescould be applied to the gate of the SGS transistor 406, depending on thelocation of the selected word line. A highest voltage of the pluralityof different voltages is applied to the gate when the selected word lineis closest to the SGS transistor 406, in one embodiment. This may helpto prevent or reduce effects of GIDL. A relatively high voltage may beapplied to the gate when the selected word line is an edge word linenear the SGS transistor 406. There may be one, two, three, or more edgeword lines in this case.

In step 2204, a program voltage is applied to the selected word linewhile applying the voltage to the gate of the SGS transistor 406.Referring to FIG. 9(D), Vpgm may be applied to the selected word lineduring the program phase.

Various other signals depicted in FIG. 9 may also be applied duringprocess 2200. Zero or more of these signals may have its value depend onthe selected word line. In one embodiment, step 2202 of process 2200 isperformed together with step 1902 of process 1900. Thus, the magnitudeof the voltage applied to both the gate of the SGS transistor 406 andthe diffusion region 431, 432 of one of the select transistors 406, 424depend on the location of the word line selected for programming, in oneembodiment.

Referring again to FIG. 18C, GIDL may also occur on the drain side ofthe NAND string. For some programming schemes GIDL induced programdisturb for the SGD transistor 424 may be most problematic for higherword lines. In one embodiment, VSGS is increased to reduce GIDL.Therefore, GIDL induced hot electron injection may be reduced oreliminated for the higher word lines. Consequently, program disturb isreduced or eliminated.

FIG. 23A depicts a flowchart of one embodiment of a process 2300 ofprogramming non-volatile storage. Process 2300 is one embodiment of step820 of process 800. In step 2302, a voltage is applied to a gate of aSGD transistor 424. The voltage depends on the location of the word linethat is selected for programming. Referring to FIG. 9(B), the magnitudeof the voltage on the drain select line SGD depends on the selected wordline in one embodiment. Note that the voltage on SGD might be alteredduring the program operation, as in the embodiment of FIG. 9(B). In oneembodiment, the value of V_SGD during the program phase depends on thelocation of the selected word line. In one embodiment, the value of V_SGduring the bit line precharge and boosting phase depends on the locationof the selected word line.

In one embodiment, V_sgd might be raised about 0.5V for edge word linesto prevent GIDL. Referring to FIG. 23B, for edge word lines from WLq tothe highest word line, Vsgd_(—)2 is higher than Vsgs_(—)1. There may beone or more of the edge word lines near the SGD transistor 424 for whichthe higher voltage is applied to prevent or reduce effects of GIDL.

In some embodiments, Vsgd does not have the same value for all of thelower word lines. In such embodiments, the value of Vsgd for the edgeword line(s) near the SGD transistor 424 is higher than the value ofVsgd for the highest middle word line. For example, Vsgd is higher whenprogramming WL63 than for WL62, such that effects of GIDL associatedwith the SGD transistor 424 are reduced or prevented.

In step 2304, a program voltage is applied to the selected word linewhile applying the voltage to the bit lines of unselected NAND strings.Referring to FIG. 9(D), Vpgm may be applied to the selected word lineduring the program phase.

Various other signals depicted in FIG. 9 may also be applied duringprocess 2300. Zero or more of these signals may have its value depend onthe selected word line.

To further reduce the risk of GIDL, during programming with a highervalue for V_SGS and/or V_SGD, all or some of the bitline biases can alsobe increased. This may help to make sure that the SGS transistor 406and/or to maintain sufficient margins V_SGD. In one embodiment, theincrease in the bit line biases are about the same as the increase inthe biases to SGS and SGD. However, the increase in the bit line biasescould be slightly less or slightly more than the increase in the biasesto SGS and SGD. FIG. 24 depicts a flowchart of one embodiment of aprocess 2400 of programming non-volatile storage. Process 2400 is oneembodiment of step 820 of process 800.

In step 2402, a voltage is applied to bit lines associated with NANDstrings that are selected for programming. The voltage depends on thelocation of the word line that is selected for programming. In oneembodiment, a higher voltage is applied to the selected bit lines whenapplying a higher voltage to the SGS transistors 406. For example, thisis used when programming the lower edge word lines. This may help toensure that the SGS transistors are cut off. In one embodiment, a highervoltage is applied to the selected bit lines when applying a highervoltage to the SGD transistors 424. For example, this is used whenprogramming the higher edge word lines.

Referring to FIG. 9(G), the magnitude of the voltage VBL_select dependson the selected word line in one embodiment. In one embodiment, thevoltage may first be applied at about the same time that the unselectedbit lines are first charges (e.g., at the start of phase 2 in FIG. 9).The voltage may be maintained during the program phase.

In one embodiment, the voltage VBL_select may be about 0V for a “normal”situation when the higher voltage is not used for V_sgs or V_sgd.However, VBL_select may be raised by about the same amount as theincrease in V_sgs or V_sgd, in one embodiment. Note that the increase inVBL_select could be slightly less or slightly more than the increase toV_sgs or V_sgd. As one example, VBL_select is increased by about 0.5Vfor when edge word lines are selected for programming. For example,VBL_select could be about 0.5V for edge word lines and about 0V formiddle word lines.

Process 2400 describes an Option A in which biases for unselected bitlines depend on the location of the selected word line and Option B iswhich they do not. In optional step 2404a, a voltage that depends on thelocation of the word line that is selected for programming is applied tobit lines associated with NAND strings that are not selected forprogramming (also referred to as inhibited NAND strings). Referring toFIG. 9(E), the magnitude of the voltage VBL_inhibit depends on theselected word line, in one embodiment.

In optional step 2404b, the voltage applied to bit lines associated withNAND strings that are not selected for programming does not depend onthe location of the word line selected for programming. Referring toFIG. 9(E), the magnitude of the voltage VBL_inhibit may be independentof the selected word line.

In one embodiment, the voltage VBL_inhibit may be about 2.2V for a“normal” situation when the higher voltage is not used for V_sgs orV_sgd. However, VBL_inhibit may be raised by about the same amount asthe increase in V_sgs or V_sgd, in one embodiment. Note that theincrease in VBL_inhibit could be slightly less or slightly more than theincrease to V_sgs or V_sgd. As one example, VBL_inhibit is increased byabout 0.5V for when edge word lines are selected for programming. Forexample, VBL_inhibit could be about 2.7V for edge word lines and about2.2V for middle word lines (assuming an increase of about 0.5V forV_sgd).

Using the higher value for VBL_inhibit along with the higher value forV_sgs may help to maintain the V_sgd margins. Note that if the V_sgdmargin is adequate then increasing VBL_inhibit may not be needed.Therefore, VBL_inhibit is not necessarily increased when increasingV_sgd for the upper edge word lines.

Process 2400 describes an Option C in which biases for bit linesassociated with NAND strings in a slow programming mode depend on thelocation of the selected word line and Option D is which they do not. Inoptional step 2406a, a voltage that depends on the location of the wordline that is selected for programming is applied to bit lines associatedwith NAND strings that are selected for slow programming. Slowprogramming may also be referred to as “quick pass write” (QPW).Referring to FIG. 9(F), the magnitude of the voltage VBL_QPW depends onthe selected word line in one embodiment.

In optional step 2406b, the voltage applied to bit lines associated withNAND strings that are not selected for slow programming does not dependon the location of the word line selected for programming. Referring toFIG. 9(F), the magnitude of the voltage VBL_QPW may be independent ofthe selected word line. Note that any combination of steps 2404 and 2406may be performed. That is, option A may be used with option C or optionD. Likewise, option B may be used with option C or option D.

In one embodiment, the voltage VBL_QPW may be about 0.7V for a “normal”situation when the higher voltage is not used for V_sgs or V_sgd.However, VBL_QPW may be raised by about the same amount as the increasein V_sgs or V_sgd, in one embodiment. Note that the increase in VBL_QPWcould be slightly less or slightly more than the increase to V_sgs orV_sgd. As one example, VBL_QPW is increased by about 0.5V for when edgeword lines are selected for programming. For example, VBL_QPW could beabout 1.2V for edge word lines and about 0.7V for middle word lines(assuming an increase of about 0.5V for V_sgs and/or V_sgd).

In step 2404, a program voltage is applied to the selected word linewhile applying the voltage from step 2402 to the bit lines of selectedNAND strings (as well as whatever voltage is applied to other bit linesin steps 2404 and 2406). Referring to FIG. 9(D), Vpgm may be applied tothe selected word line during the program phase.

Various other signals depicted in FIG. 9 may also be applied duringprocess 2300. Zero or more of these signals may have its value depend onthe selected word line. In one embodiment, process 2400 is performedwith process 2200 and 2300.

Selected Word Line Dependent Select Gate Voltage

In one embodiment, the voltage applied to the gate of a selecttransistor 406, 424 of a NAND string depends on the location of the wordline selected for programming. This may eliminate or mitigate effectscaused by drain induced barrier lowering (DIBL). If DIBL occurs, it maylower the Vth of a select transistor 406, 424. If this happens, a selecttransistor 406, 424 that should be off may turn on, at least weakly,wherein charge may leak from a boosted channel of an inhibited NANDstring. Applying a selected word line dependent voltage to the gate of aselect transistor 406, 424 may keep the transistor off, therebypreventing charge leakage from a boosted channel. Therefore, programdisturb may be reduced or eliminated. The voltage applied to the gate ofthe select transistor 406, 424 may also reduce or eliminate othereffects, such as GIDL.

In one embodiment, the voltage whose magnitude depends on the selectedword line is applied to the gate of an SGS transistor 406. In oneembodiment, a negative voltage is applied to the gate of the SGStransistor 406 for at least some positions of the selected word line.For example, a negative voltage may be applied to the gate of the SGStransistor 406 when the selected word line is a middle word line or anedge word line near the SGD transistor 424. This may prevent chargeleakage from a boosted channel that could occur as a result of DIBL.However, a voltage with a greater magnitude may be applied to the gateof the SGS transistor 406 when the selected word line is an edge wordline near the SGS transistor 406. This may prevent or reduce effects ofGIDL. Therefore, program disturb may be reduced or eliminated.

In one embodiment, the voltage whose magnitude depends on the selectedword line is applied to the gate of a SGD transistor 424. The voltagemay be selected to prevent charge leakage from a boosted channel thatcould otherwise occur as a result of DIBL.

For some boosting schemes, the channel capacitance is smaller for higherword lines. Therefore, when higher word lines are selected forprogramming, the voltage of the boosted channel may drop faster for agiven leakage current. In one embodiment, a lower magnitude voltage isused for the gate of the SGD transistor 424 when the selected word lineis closer to SGD transistor 424. In other words, the voltage maydecrease with increasing word lines. This may help compensate for thesmaller channel capacitance when programming higher word lines (e.g.,those closer to the SGD transistor 424).

FIG. 25 depicts a flowchart of one embodiment of a process 2500 ofprogramming non-volatile storage in which the voltage applied to a gateof a select transistor depends on the location of the selected wordline. Process 2500 is one embodiment of step 820 of process 800. In step2502, a voltage is applied to a gate of a select transistor 406, 424.The voltage depends on the location of the word line that is selectedfor programming. In one embodiment, a selected word line dependentvoltage is applied to the gate of an SGS transistor 406. In oneembodiment, a selected word line dependent voltage is applied to thegate of an SGD transistor 424.

Referring to FIG. 9(A), the magnitude of the voltage, V_sgs, to thesource side select line SGS depends on the selected word line in oneembodiment. In one embodiment, SGS is held at this voltage during atleast a program phase. In one embodiment, the value for the Vsgs isselected to mitigate the effects of DIBL. In one embodiment, a negativevalue is used for Vsgs when the selected word line is a middle word lineor an edge word line near the SGD transistor 424. This may prevent orreduce charge leakage of boosted channels that might otherwise occur dueto increase in Vth of the source side select transistor due to DIBL. Inone embodiment, a higher voltage is used when the selected word line isan edge word line near the SGS transistor 406. In one embodiment, V_SGSmay be about 0V to prevent GIDL when programming an edge word line nearthe SGS transistor 406. FIG. 26A shows one example of values for V_sgsfor step 2502.

Referring to FIG. 9(B), the magnitude of the voltage to the drain sideselect line SGD depends on the selected word line in one embodiment. Inone embodiment, the value for V_SGD during program phase depends on thelocation of the selected word line. In one embodiment, the value forV_SG during the bit line precharge and boosting phase depends on thelocation of the selected word line. In one embodiment, the value for theVsgd is selected to mitigate the effects of DIBL. In one embodiment,lower values are used for Vsgd for higher word lines (see FIG. 26B asone example).

In step 2504, a program voltage is applied to the selected word linewhile applying the voltage to the bit lines of unselected NAND strings.Referring to FIG. 9(D), Vpgm may be applied to the selected word lineduring the program phase. Thus, in one embodiment, process 2500 includesapplying a control voltage to the source side select line (SGS) whileapplying the program voltage, wherein the control voltage has amagnitude that depends on the location of the selected word line. In oneembodiment, process 2500 includes applying a control voltage to thedrain side select line (SGD) while applying the program voltage, whereinthe control voltage has a magnitude that depends on the location of theselected word line.

Various other signals depicted in FIG. 9 may also be applied duringprocess 2500. Zero or more of these signals may have its value depend onthe selected word line. In one embodiment, step 2502 of process 2500 isperformed together with steps 2404-2406 of process 2400 (which mayprovide protection for effects of GIDL). Thus, the magnitude of thevoltage applied to both the gate of at least one select transistor 406and/or 424 and at least the selected bit lines (and optionally theunselected bit lines and bit lines for slow programming NAND strings)depend on the location of the word line selected for programming, in oneembodiment.

FIG. 26A shows relative values for Vsgs versus word lines in accordancewith one embodiment. As noted, Vsgs may be applied to SGS during aprogram operation (see FIG. 9(A), for example). This may provide avoltage to the gates of SGS transistors 406. In this embodiment, wordlines are divided into three zones. In general, there may be two or morezones. In this embodiment, Vsgs has the highest magnitude (Vsgs_(—)1)for the lowest word lines (e.g., WL0-WLa). There may be one or more wordlines in this first zone (which may be referred to as edge word lines).In one embodiment, the value of Vsgs_(—)1 is about 0V for the edge wordlines near the SGS transistor 406. More generally, Vsgs_(—)1 is a highermagnitude that at least Vsgs_(—)2, in one embodiment. This may help toprevent or reduce effects associated with GIDL. Mitigating effects ofGIDL has been discussed above.

In one embodiment, Vsgs has a negative value for word lines other thanedge word lines near the SGS transistor 406. In other words, a negativevoltage may be applied to the gate of the SGS transistor 406 if theselected word line is a middle word line or an edge word line near theSGD transistor 424. In one embodiment, Vsgs_(—)2 and Vsgs_(—)3 arenegative. Using a negative voltage may prevent or reduce program disturbthat might otherwise occur as a result of DIBL.

However, as noted above, to prevent or mitigate effects of GIDL avoltage (e.g., Vsgs_(—)1) that is greater than the negative voltageVsgs_(—)2 may be applied to the gate of the SGS transistor 406 if theselected word line is an edge word line near the source side selecttransistor 406 (Vsgs_(—)1 could be about 0V, but a higher or lowervoltage could be used).

In one embodiment, the magnitude of Vsgs is lower (e.g., more negative)for middle word lines (e.g., WLa to WLb−1) than for edge word lines nearthe SGD transistor 424 (e.g., WLb to the highest word line). In thisexample, the value for Vsgs_(—)2 is shown as being lower than Vsgs_(—)3.However, this is not a requirement. Instead Vsgs_(—)3 could be the samevalue or lower than Vsgs_(—)2.

In one embodiment, the value for Vsgs_(—)2 is between about −0.5V toabout −1.0V. In one embodiment, the value for Vsgs_(—)3 is between about−0.5V to about −1.0V. However, note that the value could be lower orhigher for each case. In one embodiment, the value for Vsgs_(—)2 isbetween about −0.5V to about −1.0V. In one embodiment, the value forVsgs_(—)1 is about 0V; however, it could be lower or higher.

FIG. 26B shows relative values for Vsgd versus word lines in accordancewith one embodiment. As noted, Vsgd may be applied to SGD during aprogram operation (see FIG. 9(B), for example). This may provide avoltage to the gates of SGD transistors 424. In this embodiment, wordlines are divided into three zones. In general, there may be two or morezones. In this embodiment, Vsgd has the highest magnitude (Vsgs_(—)1)for the lowest word lines (e.g., WL0 to WLe−1). There may be one or moreword lines in this first zone (which may be referred to as edge wordlines).

In one embodiment, the magnitude of Vsgd is progressively lower for wordlines in higher zones. In this example, Vsgd_(—)2 is lower thanVsgd_(—)1. Likewise, Vsgd_(—)3 is lower than Vsgd_(—)3. In other words,the voltage applied to the gate of the SGD transistor 424 may be lowerif the selected word line is closer to the SGD transistor 424.

In one embodiment, the value for Vsgd_(—)1 is about 1.6V. Voltages forVsgd_(—)2 and Vsgd_(—)3 may be even lower. Note that when programminghigher word lines the capacitance of the boosted channel may be smaller,at least for some boosting schemes. Thus, using even lower voltages forhigher selected word lines may better minimize boosted charge leakage.

When a memory cell is inhibited from programming, its channel may beboosted up to a high potential (e.g., 4V to 9V depending on thedata-pattern on the neighboring cells). Also, the channel potential maydepend on which word line is selected for programming. Moreover, thechannel potential could vary from one end of the NAND string to theother, depending on the boosting mode. For example, FIG. 21D shows anEASB mode in which the channel potential for lower word lines isrelatively low when a higher word line is selected for programming.Therefore, the boosted channel voltage may depend on which word line isselected for programming.

During one embodiment of programming, the CELSRC may be at a relativelylow voltage (e.g., 0V to 2V). As noted, channels of inhibited NANDstrings may be at a significantly higher voltage. Thus for boostedchannels, a Vds may exist across the SGS transistor 242. If the Vds ishigh enough, it may lower the Vth of the SGS transistor 406 due to DIBL.The lower Vth can cause the SGS transistor 406 to turn on, which maycause boost potential leakage through the SGS transistor 406, resultingin program disturb. This phenomenon may become even worse as the size ofmemory arrays continue to scale downwards due to further scaled SGStransistor 406.

As noted, the boosted channel potential may depend on which word line isbeing programmed, at least for some boosting schemes. For some boostingschemes the channel potential at the source end of the NAND string isgreater when lower word lines are being programmed. Thus, this DIBLinduced problem could be worse when programming lower word lines. It mayalso be worse for middle word lines than for edge word lines near theSGD transistor 424. Referring back to FIG. 26A, Vsgs could be higher forthe higher word lines (compared to middle word lines) in view of theforegoing. However, as noted above, GIDL may also be a problem whenprogramming edge word lines near the SGS transistor 406. Therefore, ahigher voltage may be used when programming those edge word lines(relative to the lowest middle word lines) to combat effects of GIDL.

FIG. 27A and FIG. 27B shows possible effects of DIBL on the Vth of SGStransistors 406. Each show the Vth roll off due to DIBL. Each curveshows current versus Vgs for a different value of Vds. The label“increasing Vds” indicates which curves have the higher Vds. In FIG.27A, the curve for the highest Vds has significant Vth rolloff. FIG. 27Bis for a transistor with a smaller channel width. In this case, two ofthe curves show significant Vth roll off. Therefore, the Vth roll offproblem may become more severe with further scaling of memory arrays.

For NAND operation, the bias, Vsgd, on the SGD transistor 424 may havean optimum range under which it should be operated for normal programand inhibit operation. If Vsgd is too high or too low, it can lead tocertain issues that can either cause problems with inhibiting orprogramming the cells, leading to higher failure bit count (FBC).Therefore, there may be a Vsgd-window which dictates the values of Vsgdbias under which the SGD transistor 424 should be operated within.

A possible Vsgd window for is shown in FIG. 28. The window shows anupper cliff and a lower cliff. Possible mechanisms governing the upperand lower cliffs of the Vsgd window are described below. Curve 2801 isfor Er-x fails. Curve 2802 is for A-x fails. Curve 2803 is for B-xfails. Curve 2804 is for C-x fails.

First, the Vsgd window upper-cliff mechanism will be discussed. Thiscliff may be related to boost leakage through the SGD transistor 424leading to Er to X fails (“X” refers to any state above Erase). Toinhibit a memory cell from programming, its channel should be boosted toa high enough potential to prevent electrons from moving from thechannel to the floating gate. So that the boost potential does not leakaway through the SGD transistor 424, Vsgd should be low enough to ensurethat the SGD transistor 424 is off for boosted channels. If Vsgd is toohigh, then the SGD transistor 424 will turn on and lead to boostpotential leakage through the SGD transistor 424. This could causeprogram disturb leading to E→A fails and eventually A→B, B→C fails, ifVsgd is further raised. Thus in practice, the upper-cliff of Vsgd windowmay be determined by E→X fails.

Now, the Vsgd window lower-cliff mechanism will be discussed. The Vsgdwindow lower-cliff mechanism may be related to QPW over-programming (OP)on memory cells in QPW mode leading to A→X, B→X fails. In oneembodiment, a memory cell that is in QPW mode has its associated bitlinebiased to VBL_QPW. So that the full VBL_QPW is passed through the SGDtransistor 424 into the NAND chain, the SGD transistor 424 should stayon. If Vsgd is too low, this can cause the SGD transistor 424 to beweakly off, which may cause the channels under QPW to get weaklyboosted. A weakly boosted channel may slow down the program speed forthe associated memory cells.

Now, consider a situation under which such a memory cell on BLn isprogramming slowly while its neighboring channels (BLn−1/BLn+1) are alsoprogramming or are in QPW mode.

Assuming that NAND strings n−1 and n+1 (hereinafter, BLn−1 /n+1) areeither programming or slow programming, then those channels may be atabout 0V or 0.9V. Assume that on program Pulse #N one or both of theBLn−1/n+1 cells reach their target level. Then, on Pulse #N+1, theseBLn−1/n+1 may be biased to an inhibit voltage and their channels will beboosted up to Vboost.

Due to this sudden change in BLn−1/n+1 channel's state from a lowervoltage to a high voltage (e.g., Vboost), the SGD transistor 424 on BLncan suddenly now turn on due to the impact of neighbor bitlines and itschannel. When the BLn−1/n+1 channels are boosted, the SGD transistorsmay be OFF, the drain-side of their SGD transistors 424 may be at aboutVdd, and the source-side of their SGD transistors 424 may be at Vboost.The drain and source of the SGD transistor 424 on BLn−1/n+1 can act asside gates to the SGD transistor 424 on BLn, which may turn on thechannel under the SGD transistor 424 for BLn. This may cause the channelpotential on BLn to suddenly change from weakly boosted to VBL_QPW,which may suddenly increase the program speed for those memory cells.This increase in programming speed could lead to a large Vth increase,thereby resulting in over-programming (OP) failures. Assuming that theA-state and B-state use the QPW mode, this could specifically lead toA→B and B→C failures (otherwise referred to as QPW-OP fails).

Next, the selected word line dependence of the Vsgd window will bediscussed. FIG. 29 shows a schematic of the difference between Vsgdwindow for higher edge WLs and lower edge WLs for one possible memorydevice. For higher edge WLs, the Vsgd window is shifted down as comparedto the lower edge WLs. Thus, for such a memory device, in order to be atthe optimum Vsgd value (center of Vsgd window) during program for lowerWLs, a higher Vsgd bias may suitable to use, while for higher WLs alower Vsgd bias should be used. Other memory devices may have othercharacteristics.

First, the upper cliff will be discussed. As explained earlier, theupper-cliff of Vsgd-window may be due to boost leakage from the channelthrough the SGD transistor 424, leading to E→X fails. When programminglower WLs (e.g., WLn), all higher drain-side WLs (WLn+2 and higher) maybe in the erased state, depending on the programming scheme used. Thus,the channels of memory cells associated with the word lines on the drainside of the NAND string may be fully connected with the channel of thememory cell associated with WLn. Also, the boosting potential underneaththe erased cells may be higher than that underneath programmed cells(higher Vth cells may have lesser boost potential than lower Vth cellsunder the same Vpass). The net result is that while programming lowerWLs, the boosted channel potential may be higher and the boosted channelcapacitance may be larger. On the other hand, for higher WLsprogramming, the boost potential may be lower and the channelcapacitance may be smaller.

At Vsgd-window upper-cliff, the boost leakage can be envisioned as acharged capacitor (channel in this case) leaking away during theprogram-time. The potential for a smaller capacitor leaks away muchfaster than that for a larger capacitor. Thus, for higher WLs, theleakage of the boost potential within the program-time may be largerthan for lower WLs, and hence the upper-Vsgd margin may be smaller. Forthe same reason, at a given higher Vsgd value, higher WLs may have agreater FBC than lower WLs (see FIG. 29).

Next, the lower cliff will be discussed. As explained earlier, thelower-cliff of Vsgd-window may be due to QPW-OP on the cells under QPWmode. The QPW-OP for a given NAND string may occur when its neighboringNAND strings channels suddenly switch from program to inhibit which mayresult in its SGD transistor 424 suddenly turning on due to highpotential on the drain and source side of the SGD transistors 424 ofneighbor NAND strings. The drain and source side of the neighbor SGDtransistors 424 may act as side gates for SGD transistor 424 on NANDstring n. The net impact of this phenomena may be dependent on the netpotential swing that occurs on the drain/source of BLn−1/n+1 SGDtransistors 424. Once the BLn−1/n+1 are inhibited, drain-side of theirSGD transistors 424 may be fixed at Vbl_inhibit, and the source side maybe at Vboost. Thus, if Vboost is high, then more cells may be impactedby QPW-OP. As mentioned above, the boost potential (Vboost) may belarger during lower WLs programming. Thus, the QPW-OP issue may impactlower WLs more than the higher WLs, and hence lower-WLs may have smallermargin on lower-side of Vsgd window. For the same reason, at lower Vsgdvalues, lower WLs tend to have more FBC (see FIG. 29).

Thus the lower-cliff and upper-cliff of Vsgd window tend to haveopposite WL-dependence as shown in FIG. 29. The Vsgd window for higherWLs may be shifted lower as compared to lower WLs. Therefore, in oneembodiment, the overall Vsgd window is maximized by using a lower Vsgdwhen programming higher WLs, and a higher Vsgd when programming lowerWLs. FIG. 26B shows one embodiment of such a scheme. As noted, there maybe any number of “zones,” each of which may contain any number of wordlines.

FIGS. 30A and 30B show Fail Bit Count (FBC) versus word line fordifferent values of Vsgd. FIG. 30A shows A to X fails for lower valuesof Vsgd. Vsgd1 is the very lowest followed by Vsgd2 and Vsgd3. FIG. 30Bshows E to X fails for higher values of Vsgd. Vsgd6 is the very highestwith Vsgd5 and Vsgd4 being lower in magnitude. All Vsgd in FIG. 30B aresignificantly higher than each of the Vsgd in FIG. 30A.

As shown in FIG. 30A, the lower-cliff of Vsgd window may be dominated byA→X fails. FIG. 30B shows that the upper-cliff is dominated by E→Xfails. FIG. 30A shows that for the lower-cliff, lower WLs a have smallermargin. FIG. 30B shows that for the upper-cliff, higher WLs have asmaller margin. Therefore, in one embodiment, a lower Vsgd value is usedduring higher WLs programming and higher Vsgd value is used during lowerWLs programming, in order to maximize the net Vsgd window width.

Note that the highest word line may have an exceptionally high FBC.Thus, in one embodiment, a unique low Vsgd value for the highest WL isused. In other words, the value for Vsgd when programming the highestword line is lower than for any other word line, in one embodiment. Inone embodiment, a unique low Vsgd value is used for the highest edgeword lines, such as the highest two, three, or more word lines.

One embodiment includes a method of operating non-volatile storage,comprising applying a programming voltage to a selected word line thathas a duration that depends on the width of the selected word line.

One embodiment includes a non-volatile storage device, comprising aplurality of non-volatile storage elements arranged as NAND strings, aplurality of word lines associated with the plurality of non-volatilestorage elements, and one or more managing circuits in communicationwith the plurality of word lines. The one or more managing circuitsapply a programming voltage to a selected word line of the plurality ofword lines. The programming voltage has a duration that depends on thewidth of the selected word line.

One embodiment includes a method of operating non-volatile storage,comprising programming non-volatile storage elements associated with aplurality of word lines. The non-volatile storage elements are arrangedas a plurality of NAND strings. The plurality of word lines are arrangedfrom lowest to highest from a first end to a second end of the pluralityof NAND strings. The programming includes applying a programming signalfor a given program loop having a shorter pulse width when either thelowest word line or the highest word line is selected for programmingthan the pulse width used to program at least one other word line of theplurality of word lines.

One embodiment includes a non-volatile storage device, comprising aplurality of non-volatile storage elements arranged as NAND strings, aplurality of word lines associated with the plurality of non-volatilestorage elements, and one or more managing circuits in communicationwith the plurality of word lines. The word lines are arranged fromlowest to highest from a first end to a second end of the plurality ofNAND strings. The one or more managing circuits program the plurality ofnon-volatile storage elements using a program signal having a pulsewidth. The one or more managing circuits apply a programming signal fora given program loop having a shorter pulse width when either the lowestor highest word line is selected for programming than the pulse widthused to program at least one other word line.

One embodiment includes a method of operating non-volatile storage,comprising the following. Non-volatile storage elements associated witha plurality of word lines in a first block are programmed. Thenon-volatile storage elements are arranged as a plurality of NANDstrings each having a first end and a second end, each of the word lineshaving a position between the first end and the second end. A finalprogram voltage or a number of program loops that it takes to completethe programming of each of the word lines in the first block isdetermined. A pulse width duration is determined for each position ofthe word lines based on the final program voltage or the number ofprogram loops. Word lines in other blocks are programmed using the pulsewidth duration that was determined for each position.

One embodiment includes a method of operating non-volatile storagehaving a plurality of NAND strings. Each NAND string may include aplurality of non-volatile storage elements above a channel, a firstselect transistor at a first end of the NAND string, and a second selecttransistor at a second end of the NAND string. The first and secondselect transistors each may have a diffusion region on the opposite sideof the select transistor from the channel region. The method comprisesapplying a voltage to the diffusion region of at least one of the firstselect transistors. The NAND strings are associated with a plurality ofword lines. The magnitude of the voltage applied to the diffusion regiondepends on the location of a selected word line on the plurality of NANDstrings. The method also includes applying a program voltage to theselected word line while applying the voltage to the diffusion region.

One embodiment includes a non-volatile storage device comprising aplurality of NAND strings, a plurality of word lines associated with theplurality of NAND strings, and one or more managing circuits incommunication with the plurality of non-volatile NAND strings, and theplurality of word lines. Each NAND string has a plurality ofnon-volatile storage elements over a channel, a first select transistorat a first end of the NAND string, and a second select transistor at asecond end of the NAND string. The first and second select transistorseach have a diffusion region on the opposite side of the selecttransistor from the channel of the NAND string. The one or more managingcircuits apply a voltage to the diffusion region of at least one of thefirst select transistors. The magnitude of the voltage applied to thediffusion region depends on the location of a selected word line on theplurality of NAND strings. The one or more managing circuits apply aprogram voltage to the selected word line while applying the voltage tothe diffusion region of at least one of the first select transistors.

One embodiment includes a method of operating non-volatile storagehaving a plurality of NAND strings associated with a plurality of wordlines. Each of the plurality of NAND strings are associated with a firstcontact at a first end of a given NAND string and a second contact at asecond end of a given NAND string. The method comprises applying avoltage that depends on the location of a selected word line of theplurality of word lines to the first contact associated with at leastunselected NAND strings of the plurality of NAND strings; and applying aprogram voltage to the selected word line while applying the voltage.

One embodiment includes a non-volatile storage device, comprising aplurality of NAND strings, each of the NAND strings have a plurality ofnon-volatile storage elements, a drain side select transistor, and asource side select transistor; a plurality of word lines associated withthe plurality of NAND strings; a common source line coupled to thesource side select transistors of the NAND strings; a plurality of bitlines, each of the bit lines is coupled to the drain side selecttransistor associated with one of the NAND strings; and one or moremanaging circuits in communication with the plurality of NAND strings,the plurality of word lines, the common source line, and the pluralityof bit lines. The one or more managing circuits apply a first voltagethat depends on the location of a selected word line of the plurality ofword lines to either the bit lines associated with the drain side selecttransistors of inhibited NAND strings or the source line associated withthe source side select transistors. The one or more managing circuitsapply a program voltage to the selected word line while applying thefirst voltage.

One embodiment includes a method of operating non-volatile storagehaving a plurality of NAND strings and a plurality of word linesassociated with the plurality of NAND strings. The method comprisesapplying a voltage to a common source line having a magnitude thatdepends on the location of a selected word line on the plurality of NANDstrings; and applying a program voltage to the selected word line whileapplying the voltage to the common source line.

One embodiment includes a method of operating non-volatile storage thatincludes a plurality of NAND strings and a plurality of word lines. TheNAND strings each have a first select transistor at a first end of theNAND string and a second select transistor at a second end of the NANDstring. The method comprises applying a voltage to a gate of the firstselect transistor of a first of the plurality of NAND strings that has amagnitude that depends on the location of a selected word line of theplurality of word lines; and applying a program voltage to the selectedword line while applying the voltage to the gate of the first selecttransistor.

One embodiment includes a non-volatile storage device, comprising aplurality of non-volatile NAND strings, each NAND string having aplurality of non-volatile storage elements and a first select transistorat a first end of the NAND string and a second select transistor at asecond end of the NAND string, each of the first and second selecttransistor having a gate; a plurality of word lines associated with theplurality of NAND strings; a first select line coupled to the gates ofthe first select transistors; a second select line coupled to the gatesof the second select transistors; and one or more managing circuits incommunication with the plurality of NAND strings, the plurality of wordlines, the first select line, and the second select line. The one ormore managing circuits apply a program voltage to a selected word lineof the plurality of word lines. The one or more managing circuits applya voltage to the first select line while applying the program voltage.The voltage applied to the first select line has a magnitude thatdepends on the location of the selected word line.

One embodiment includes a method of operating non-volatile storage,comprising programming non-volatile storage elements arranged as NANDstrings. The NAND strings are associated with a plurality of word lines,a drain side select line, and a source side select line. Each NANDstring has a drain side select transistor coupled to the drain sideselect line and a source side select transistor coupled to the sourceside select line. The programming includes applying a program voltage toa selected word line of the plurality of word lines, and applying acontrol voltage to either the drain side select line or the source sideselect line while applying the program voltage. The control voltage hasa magnitude that depends on the location of the selected word line onthe plurality of NAND strings.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit embodiments to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. The describedembodiments were chosen in order to best explain principles andpractical application, to thereby enable others skilled in the art tobest utilize the various embodiments and with various modifications asare suited to the particular use contemplated. It is intended that thescope be defined by the claims appended hereto.

We claim:
 1. A method of operating non-volatile storage that includes aplurality of NAND strings and a plurality of word lines, the NANDstrings each having a source side select transistor at a first end ofthe NAND string and a drain side select transistor at a second end ofthe NAND string, the method comprising: applying a voltage to a gate ofthe source side select transistor of a first of the plurality of NANDstrings that has a magnitude that depends on the location of a selectedword line of the plurality of word lines; and applying a program voltageto the selected word line while applying the voltage to the gate of thesource side select transistor.
 2. The method of claim 1, wherein theapplying a voltage to a gate of the source side select transistorincludes applying a negative voltage to the gate of the source sideselect transistor.
 3. The method of claim 1, wherein the applying avoltage to a gate of the source side select transistor includes applyingone of a plurality of different voltages to the gate of the source sideselect transistor, a highest voltage of the plurality of differentvoltages is applied when the selected word line is closest to the sourceside select transistor.
 4. The method of claim 1, wherein the applying avoltage to a gate of the source side select transistor includes:applying a negative voltage to the gate of the source side selecttransistor if the selected word line is a middle word line or an edgeword line near the drain side select transistor; and applying a voltagethat is greater than the negative voltage to the gate of the source sideselect transistor if the selected word line is an edge word line nearthe source side select transistor.
 5. The method of claim 1, furthercomprising: applying a voltage to a gate of the drain side selecttransistor of the first NAND string that has a magnitude that depends onthe location of the selected word line while applying the programvoltage to the selected word line, including applying a lower voltage tothe gate of the drain side select transistor if the selected word lineis closer to the drain side select transistor.
 6. The method of claim 1,further comprising: applying a voltage to a gate of the drain sideselect transistor of the first NAND string that has a magnitude thatdepends on the location of the selected word line while applying theprogram voltage to the selected word line, including applying one of aplurality of different voltages to the gate of the drain side selecttransistor, a highest voltage of the plurality of different voltages isapplied when the selected word line is closest to the drain side selecttransistor.
 7. The method of claim 1, wherein each of the NAND stringsis associated with a bit line, further comprising applying a voltage tothe bit lines associated with selected NAND strings of the plurality ofNAND strings that depends on the location of the selected word linewhile applying the program voltage.
 8. The method of claim 7, whereinthe applying a voltage to the bit lines associated with the selectedNAND strings includes: applying a first bit line voltage that depends onthe position of the selected word line to the bit lines associated withNAND strings that are selected for programming while applying theprogram voltage.
 9. The method of claim 8, further comprising: applyinga second bit line voltage to the bit lines associated with NAND stringsthat are selected for slower programming while applying the programvoltage, the second bit line voltage depends on the position of theselected word line; and applying a third bit line voltage to the bitlines of unselected NAND strings while applying the program voltage, thethird bit line voltage depends on the position of the selected wordline.
 10. A non-volatile storage device, comprising: a plurality ofnon-volatile NAND strings, each NAND string having a plurality ofnon-volatile storage elements and a source side select transistor at afirst end of the NAND string and a drain side select transistor at asecond end of the NAND string, each of the source and second drainselect transistors having a gate; a plurality of bit lines associatedwith the plurality of NAND strings; a plurality of word lines associatedwith the plurality of NAND strings; a first select line coupled to thegates of the source select transistors; a second select line coupled tothe gates of the drain select transistors; and one or more managingcircuits in communication with the plurality of NAND strings, theplurality of word lines, the plurality of bit lines, the first selectline, and the second select line, the one or more managing circuitsapply a program voltage to a selected word line of the plurality of wordlines, the one or more managing circuits apply a voltage to the firstselect line while applying the program voltage, the voltage applied tothe first select line has a magnitude that depends on the location ofthe selected word line.
 11. The non-volatile storage device of claim 10,wherein the one or more managing circuits applying a negative voltage tothe first select line while applying the program voltage.
 12. Thenon-volatile storage device of claim 10, wherein the one or moremanaging circuits apply a plurality of different voltages to the firstselect line depending on the position of the selected word line, ahighest voltage of the plurality of different voltages is applied to thefirst select line when the selected word line is closest to the firstselect line.
 13. The non-volatile storage device of claim 10, whereinthe one or more managing circuits apply a negative voltage to the firstselect line if the selected word line is a middle word line or an edgeword line near the second select line, the one or more managing circuitsapply a voltage that is greater than the negative voltage to the firstselect line if the selected word line is an edge word line near thefirst select line.
 14. The non-volatile storage device of claim 10,wherein the one or more managing circuits apply a voltage to the secondselect line while applying the program voltage to the selected word linethat has a magnitude that depends on the location of the selected wordline, the one or more managing circuits apply a lower voltage to thesecond select line while applying the program voltage if the selectedword line is closer to the second select line.
 15. The non-volatilestorage device of claim 10, wherein the one or more managing circuitsapply a voltage to the second select line while applying the programvoltage to the selected word line that has a magnitude that depends onthe location of the selected word line, the one or more managingcircuits, the one or more managing circuits apply one of a plurality ofdifferent voltages to the second select line while applying the programvoltage, a highest voltage of the plurality of different voltages isapplied if the selected word line is closest to the second select line.16. The non-volatile storage device of claim 10, wherein the one or moremanaging circuits apply a voltage to the bit lines associated withselected NAND strings of the plurality of NAND strings that depends onthe location of the selected word line while applying the programvoltage.
 17. The non-volatile storage device of claim 10, wherein theone or more managing circuits apply a first bit line voltage thatdepends on the position of the selected word line to bit linesassociated with NAND strings that are selected for programming whileapplying the program voltage.
 18. The non-volatile storage device ofclaim 17, wherein the one or more managing circuits apply a second bitline voltage to the bit lines associated with NAND strings that areselected for slower programming while applying the program voltage, thesecond bit line voltage depends on the position of the selected wordline, the one or more managing circuits apply a third bit line voltageto the bit lines of unselected NAND strings while applying the programvoltage and the voltage to the first select line, the third bit linevoltage depends on the position of the selected word line.
 19. A methodof operating non-volatile storage that includes a plurality of NANDstrings and a plurality of word lines, the NAND strings each having asource side select transistor at a first end of the NAND string and adrain side select transistor at a second end of the NAND string, themethod comprising: applying an inhibit voltage to a bit line associatedwith a first NAND string of the plurality of NAND strings; applying avoltage to a gate of the drain side select transistor of the first NANDstring that has a magnitude that depends on the location of a selectedword line of the plurality of word lines, including applying a highervoltage to the gate of the drain side select transistor if the selectedword line is closer to the drain side select transistor to keep thedrain side select transistor off; and applying a program voltage to theselected word line while applying the voltage to the gate of the drainside select transistor.
 20. A non-volatile storage device, comprising: aplurality of non-volatile NAND strings, each NAND string having aplurality of non-volatile storage elements and a source side selecttransistor at a first end of the NAND string and a drain side selecttransistor at a second end of the NAND string, each of the source anddrain select transistors having a gate; a plurality of word linesassociated with the plurality of NAND strings; a plurality of bit lines,each of the NAND strings is associated with one of the bit lines; afirst select line coupled to the gates of the source select transistors;a second select line coupled to the gates of the drain selecttransistors; and one or more managing circuits in communication with theplurality of word lines, the first select line, the second select line,and the plurality of bit lines, the one or more managing circuits applyan inhibit voltage to a first bit line associated with a first NANDstring of the plurality of NAND strings, the one or more managingcircuits apply a voltage to a gate of the drain side select transistorof the first NAND string that has a magnitude that depends on thelocation of a selected word line of the plurality of word lines,including applying a higher voltage to the gate of the drain side selecttransistor if the selected word line is closer to the drain side selecttransistor to keep the drain side select transistor off, the one or moremanaging circuits apply a program voltage to the selected word linewhile applying the voltage to the gate of the drain side selecttransistor.
 21. A method of operating non-volatile storage that includesa plurality of NAND strings and a plurality of word lines, the NANDstrings each having a source side select transistor at a first end ofthe NAND string and a drain side select transistor at a second end ofthe NAND string, the method comprising: applying an inhibit voltage to abit line associated with a first NAND string of the plurality of NANDstrings; applying a voltage to a gate of the drain side selecttransistor of the first NAND string that has a magnitude that depends onthe location of a selected word line of the plurality of word lines toprevent DIBL; and applying a program voltage to the selected word linewhile applying the voltage to the gate of the drain side selecttransistor.
 22. The method of claim 21, wherein applying a voltage to agate of the drain side select transistor includes: applying a voltage tothe drain side select transistor when programming the highest word linethat is lower in magnitude from the voltage applied to the drain sideselect transistor when programming any other word line.
 23. The methodof claim 1, further comprising: applying an inhibit voltage to a firstbit line that is associated with the first NAND string while applyingthe program voltage.
 24. The non-volatile storage device of claim 10,wherein the one or more managing circuits apply an inhibit voltage to afirst bit line associated with an unselected NAND string while applyingthe program voltage.
 25. The method of claim 1, wherein: the pluralityof NAND strings are arranged in a three-dimensional memory structure.26. The non-volatile storage device of claim 10, wherein: the pluralityof NAND strings are arranged in a three-dimensional memory structure.27. The method of claim 19, wherein: the non-volatile storage comprisesa three-dimensional memory array, the three-dimensional memory arraycomprises the plurality of NAND strings.
 28. The non-volatile storagedevice of claim 20, wherein: the non-volatile storage device comprises athree-dimensional memory array, the three-dimensional memory arraycomprises the plurality of non-volatile NAND strings.
 29. The method ofclaim 21, wherein: the non-volatile storage comprises athree-dimensional memory array, the three-dimensional memory arraycomprises the plurality of NAND strings.